【精品】vhdl双语教学第6章(可编辑.ppt
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1、VHDL双语教学第6章2023/3/14【可编辑】AgendaOther Features in VHDLGenerateAssertFunctionOverloadingFILEIOGenerate Example(1)ram32:ram_0:static_ram portmap(cs_b,we_b,oe_b,abus(7downto0),dbus(7downto0);ram_1:static_ram portmap(cs_b,we_b,oe_b,abus(7downto0),dbus(15downto8);ram_2:static_ram portmap(cs_b,we_b,oe_b,ab
2、us(7downto0),dbus(23downto16);ram_3:static_ram portmap(cs_b,we_b,oe_b,abus(7downto0),dbus(31downto24);endgenerateram32;RAM0RAM1RAM2RAM38-bitBus8-bitBus8-bitBus8-bitBus32-bitBus8-bit addr8-bit addr8-bit addr8-bit addrGenerate Example(2)ram32:foriin3downto0generateram:static_ram portmap(cs_b,we_b,oe_b
3、,abus(7downto0),dbus(8*i+7downto8*i);endgenerateram32;RAM0RAM1RAM2RAM38-bitBus8-bitBus8-bitBus8-bitBus32-bitBus8-bit addr8-bit addr8-bit addr8-bit addrGenerateLabel:forParameterNameinRangegenerateConcurrentStatements.endgenerateLabel;Label:ifConditiongenerateConcurrentStatements.endgenerateLabel;Age
4、ndaGenerateAssertFunctionOverloadingFILEIOAssertDefinitionLabel:assertConditionreport StringExpressionseverity Expression;Notel lThe message is written when the Condition isThe message is written when the Condition is False!lThedefaultstringforreportreportclauseis“Assertionviolation”lThedefaultstrin
5、gforseverity severity clauseis“ERROR”Concurrent Assertions&Concurrent Procedure CallsLabel:assertconditionreporterror_stringseverityseverity_value;Label:processbeginassertconditionreporterror_stringseverityseverity_value;wait sensitivity_clause;end processLabel;concurrent assertionsconcurrent proced
6、ure callsAssert Example(1)assertnot(Reset=0 and Set=0)reportR-S conflictseverityFailure;Assert Example(2)Severity_leveltypeseverity_levelis(note,warning,error,failure);(Instandard.vhd)AgendaGenerateAssertFunction OverloadingFILEIOFunction OverloadingVHDLallowstwosubprogramstohavethesame name,provide
7、dthenumber or base types of parameters differsFunction Overloading(Example 1)functionFoo(value:bit)returnboolean;functionFoo(value:std_logic)returnboolean;Function Overloading(Example 2)function+(arg1,arg2:STD_LOGIC_VECTOR)returnSTD_LOGIC_VECTOR;function+(L,R:UNSIGNED)returnUNSIGNED;function+(L,R:SI
8、GNED)returnSIGNED;Function Overloading(Example 3)FUNCTION+(arg1,arg2:STD_LOGIC_VECTOR)RETURN STD_LOGIC_VECTOR ISCONSTANTml:INTEGER:=maximum(arg1length,arg2length);VARIABLElt:STD_LOGIC_VECTOR(1TOml);VARIABLErt:STD_LOGIC_VECTOR(1TOml);VARIABLEres:STD_LOGIC_VECTOR(1TOml);VARIABLEcarry:STD_LOGIC:=0;VARI
9、ABLEa,b,s1:STD_LOGIC;-Unsignedarithmeticadditionoftwovectors.MSBisLeft.ATTRIBUTEsynthesis_returnOFres:VARIABLEISADD;BEGINlt:=zxt(arg1,ml);rt:=zxt(arg2,ml);FORiINresreverse_rangeLOOPa:=lt(i);b:=rt(i);s1:=a+b;res(i):=s1+carry;carry:=(aANDb)OR(s1ANDcarry);ENDLOOP;RETURNres;END;FUNCTION+(arg1,arg2:UNSIG
10、NED)RETURN UNSIGNED ISCONSTANTml:INTEGER:=maximum(arg1length,arg2length);VARIABLElt:UNSIGNED(1TOml);VARIABLErt:UNSIGNED(1TOml);VARIABLEres:UNSIGNED(1TOml);VARIABLEcarry:STD_LOGIC:=0;VARIABLEa,b,s1:STD_LOGIC;-Unsignedarithmeticadditionoftwovectors.MSBisLeft.ATTRIBUTEsynthesis_returnOFres:VARIABLEISAD
11、D;BEGINlt:=zxt(arg1,ml);rt:=zxt(arg2,ml);FORiINresreverse_rangeLOOPa:=lt(i);b:=rt(i);s1:=a+b;res(i):=s1+carry;carry:=(aANDb)OR(s1ANDcarry);ENDLOOP;RETURNres;END;Function Overloading(Example 4)function+(a,b:byte)returnbyteisbeginreturnint_to_byte(byte_to_int(a)+byte_to_int(b);end+;X1000_0010+X0000_FF
12、D0+(X1000_0010,X0000_FFD0)AgendaGenerateAssertFunctionOverloadingFILE IOl lText FileText FilelBinaryFileRead/Write Text File12123122341Awfe011100010-Disk File1001011011Line variableReadLine()Read()Data Object12123122341Awfe011100010-Disk File1001011011Line variableWriteLine()Write()Data ObjectRead F
13、rom Text FileWrite To Text FileRead/Write Text File StepsStep1 Defineuserdataobject,DataObjStep2 DefineLineobject,LineObjvariable LineObj:line;Step2 DefineTextFileobject,FileObj file FileObject:text is in FileName;file FileObject:text is out FileName;Step4 Read/WriteDatalReadreadLine(FileObj,LineObj
14、);read(LineObj,DataObj);lWriteWrite(LineObj,DataObj);WriteLine(FileObj,LineObj);Read/Write Text File(Example)libraryieee;useieee.std_logic_1164.all;usestd.textio.all;entitytext_file_readisendtext_file_read;architecturetext_file_read_aoftext_file_readisbeginprocessvariablebv:bit_vector(3downto0);vari
15、able ln_in:line;variable ln_out:line;file file_in:text is in text1.dat;file file_out:text is out text2.dat;beginloopexitwhenendfile(file_in);readline(file_in,ln_in);read(ln_in,bv);write(ln_out,bv);writeline(file_out,ln_out);endloop;wait;endprocess;endtext_file_read_a;11111010text1.dat11111010text2.d
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