【精品】soc设计方法与实现第八章 综合与sta（可编辑.ppt

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1、SoC设计方法与实现第八章 综合与STAOutlinesLogicSynthesis&CompilingStrategyPhysicalSynthesis&CompilingStrategySynthesisUsingSynopsyssDesignCompiler(DC)StaticTimingAnalysis(STA)STAUsingSynopsyssPrimetime(PT)StatisticalStaticTimingAnalysis(SSTA)WhatLogicSynthesisDo?lGenerate netlist with user specified library(trans

2、late&mapping)lMassage netlist to meet release criteria(optimization)SelectingandUsingaCompilingStrategyCompilingStrategy:Top-downThetop-leveldesignandallitssubdesignarecompiledtogetherAdvantages:nOnlytoplevelconstraintsareneedednBetterresultsduetooptimizationacrossentiredesignDisadvantagesnLongcompi

3、letimesnIncrementalchangestothesub-blocksrequirecompletere-synthesisnToollimitforhandle“large”designOptimizingDesignArchitecturaloptimizationne.g.SelectingDesignWareimplementationsLogic-LeveloptimizationnStructuring-forreduceddesignareanFlattening-forspeedoptimizationGate-LeveloptimizationnDelayopti

4、mizationnDesignrulefixingnAreaoptimizationTimingcorrectionismosteffectivewithplacementinformationnE.g.,PhysicalsynthesisLargeCircuitOptimizationProblemsnRun-time becomes intractablenQuality of solution drops sharply Suggestion nCircuit partition using bottom-up synthesis strategyn“Timing budget”synt

5、hesis strategy nTop-down(RTL-to-gate)to get the timing budget for each module,then do synthesis optimization on each module,followed by gate-to-gate synthesis optimization for the entire designPreserveClockandResetNetworksClocknetworksaretypicallydonebyClockTreeSynthesis(CTS),notbysynthesizeAsynchro

6、nousresetnetworksarealsotypicallytreatedasspecialnetworks,w/insertingappropriatebuffersPreserveclock&resetnetworknExample：SynopsyssDesignCompliler,set_dont_touch_network OutlinesLogicSynthesis&CompilingStrategyPhysicalSynthesis&CompilingStrategySynthesisUsingSynopsyssDesignCompiler(DC)StaticTimingAn

7、alysis(STA)STAUsingSynopsyssPrimetime(PT)StatisticalStaticTimingAnalysis(SSTA)WireDelayandDeviceDelayChallengeforLogicSynthesisToolForprocess0.18umorless,wiredelaylargerthandevicedelaynWiresareclosertogethernWiresarenarrowerStatisticalwireloadmodel(set_wire_load)nolongerworksPhysical ViewLogical Vie

8、wPhysicalSynthesisPhysicalsynthesiscombinesSynthesis,PlacementandStatictiminganalysiswithrouteestimationtogetherItdoesnotusewireload-modelsnThedelayiscalculatedbasedonplacementratherthanfanoutBenefitsnFrontenddesignerscanconsiderphysicaleffectsearlierinthedesignprocessnBettersynthesisresultsleadfast

9、ertimingclosurePhysicalConstraintsPhysicalsynthesisrequirestheconstraints:nPhysicalsizeofthemacro/chipnPinlocationsnGroupinginformationPhysicalSynthesisFlowRTL-to-placed-gateflownIntputs:RTL,floorplan,timingconstraint,libsetupfilenCouldtakeextremelylongtime,especiallyforlargedesigngate-to-placed-gat

10、eflownInputs:gatelevelnetlist,floorplan,timingconstraint,libsetupfilenOptimizingexistinggatelevelnetlistaccordingtotheplacementnRecommendedflowforfasttimingclosureOutlinesLogicSynthesis&CompilingStrategyPhysicalSynthesis&CompilingStrategySynthesisUsingSynopsyssDesignCompilerStaticTimingAnalysis(STA)

11、STAUsingSynopsyssPrimetimeStatisticalStaticTimingAnalysis(SSTA)SynopsysDCFlowSpecifyLibraries Target_libraryThe technology libraries which contain standard cells that Design Compiler maps to during optimizationLink_libraryAll technology libraries which contain hardmacros,standard cells that Design C

12、ompiler uses to resolve cell references Synthetic_libraryA DesignWare library is a collection of reusable circuit-design building blocks(component).Technology independent.Symbol_librarySymbol libraries contain definitions of the graphic symbols that represent library cells in the design schematics.D

13、efiningDesignEnvironmentDefining the Operating ConditionsDefining Wire Load ModelsModeling the System InterfaceDesignConstraintsDesignruleconstraintsnset_max_transitionnset_max_fanoutnset_max_capacitanceDesignoptimizationconstraintsnset_input_delaynset_output_delaynset_max_areaHintsHighfanoutnets/eq

14、ualdelaypathcanbeachievedinDC:set_min_delay,set_max_delaynExample:data/addressbusesforexternalSDRAMinterfaceDefiningClockcreate_clocknameperiodwaveformget_portsset_clock_latency(insertiondelay)set_clock_uncertainty(skew)set_clock_transition(transitiontime)create_generated_clockSpecifyingI/OTimingReq

15、uirementsInputDelayAninputdelayisthespecificationofanarrivaltimeatinputportrelativetoaclockedge.OutputdelayAnoutputdelayrepresentsanexternaltimingpathfromanoutputporttoaregister.qqset_input_delay 4.5 clock PHl1 IN1set_input_delay 4.5 clock PHl1 IN1qqset_output_delay 4.3 clock PHl1 OUT1set_output_del

16、ay 4.3 clock PHl1 OUT1SpecialPathControlSet_false_pathnToignoreaparticularpathfortimingoroptimizationSet_multicycle_pathnToinformDCregardingthenumberofclkcyclesaparticularpathrequired.Defaultis1cyclepathSet_max_delay/set_min_delaynDefinethemax/mindelayrequiredforaparticularpathFalsePathAfalsepathist

17、hepathwhichisneversensitized/caredduetothelogicconfiguration,expecteddatasequence,oroperatingmode.ItwillnotbecheckedinSTAe.g.set_false_pathfromtoMulti-cyclePathAmulti-cyclepathisApathdesignedtotakemorethanoneclockcyclefromlaunchtocapturee.g.set_multicycle_path2setupfromA-toBRunDesignCompiler(dc)Sugg

18、esttohave3files:nStartupfilen.synopsys_dc.setupnConstraintfilesnconstraints.tclnDCscriptsndc_script.tclCodingGuidelinesforSynthesisScriptsAllscriptsshouldbeginwithaheaderdescribingfile,purpose,author,revisionCommentsshouldbeusedextensivelyAllscriptsshouldbeunderrevisioncontrolNohard-codednumbers,dat

19、avalues,orfilenamesshouldbeburiedinthebodyofthescriptsNohard-codedpathsshouldappearinanyscriptsScriptsshouldbeassimpleastheycanbeandstillmeettheirobjectivesCommoncommandssuchasdefininglib,searchpathsshouldbeinasinglesetupfile,.synopsys_dc.setupRecommendationAlwaysreadthelogfiletofind“Warning”Alwaysu

20、seanalyze&elaborateAlwaysuselinktomakesurenothingismissingAlwaysusecheck_designandcheck_timingandunderstandthewarningmessagesAlwaysstartwithadefaultcompileAlwayssavethedesignwiththe-hierarchyoptionAlwaysputconstraintsintoaseparatescriptfileandcallitfromyourmainscriptUse-syntax_check&-context_checkpr

21、iortorunningascriptforthefirsttimeFixallcombinatorialfeedbackloopsreportedbyDCExample.synopsys_dc.setup(tclformat)#/*.synopsys_dc.sretup*/#/*/setsearch_pathcontact$search_pathlist“.”“/usr/golden/library/std_cells”settarget_librarylistex25_worst.dbex25_best.dbsetlink_librarylist“*”,ex25_worst.dbex25_

22、best.dbsetsymbol_librarylistex25.sdbdefine_name_rulesBORGallowed“A-Za-z0-9”-first_restricted“_”-last_restricted“_”-max_length30-mapcontactlist“*cell*”mycell”list“*-return”myreturn”setbus_naming_style%s%dsetverilogout_no_tritruesetverilogout_show_unconnected_pinstrue#/*ForDFT:definescanstyle*/set tes

23、t_default_scan_style multiplexer_flip_flopExample of create_clockcreate_clock-name SYS_CLK-period 9-waveform list 0 create_clock-name SYS_CLK-period 9-waveform list 0 4 get_pins pll_clk4 get_pins pll_clkset_clock_uncertainty-setup 0.5 SYS_CLKset_clock_uncertainty-setup 0.5 SYS_CLKset_clock_uncertain

24、ty-hold 0.5 SYS_CLKset_clock_uncertainty-hold 0.5 SYS_CLKset_clock_latency 4-min get_clocks SYS_CLKset_clock_latency 4-min get_clocks SYS_CLKset_clock_latency 4.5-max get_clocks SYS_CLKset_clock_latency 4.5-max get_clocks SYS_CLKset_clock_transition 0.5 get_clocks SYS_CLKset_clock_transition 0.5 get

25、_clocks SYS_CLKset_dont_touch_network get_clocks SYS_CLKset_dont_touch_network get_clocks SYS_CLKSet_ideal_network get_clocks SYS_CLKSet_ideal_network get_clocks SYS_CLKExample of create_generated clockExample of create_generated clockFor a clk from a divider:create_generated_clock-divide_by 2-sourc

26、e get_pins pll_clk-name 48MCLK get_pins crc/crm_clkc_clkgen/usb_clkset_clock_uncertainty-setup 0.5 48MCLKset_clock_uncertainty-hold 0.5 48MCLKset_clock_latency 4-min get_clocks 48MCLKset_clock_latency 4.5-max get_clocks 48MCLKset_clock_transition 0.5 get_clocks 48MCLKset_dont_touch_network get_clock

27、s 48MCLKSet_ideal_network get_clocks 48MCLKExample-constraint.tcl#/*/#/*Clockspecificationanddesignconstraints*/create_clockperiod33waveformlist016.5tckset_dont_touch_networklisttcktrstset_ideal_networklisttcktrstset_clock_latency2.0tckset_clock_uncertaintysetup3.0tckset_driveing_celllib_cellBUFF1Xp

28、inZall_inputsset_input_delay20.0clocktckmaxall_inputsset_output_delay10.0clocktckmaxall_outputsset_max_area0Example-dc_script.tcl#/*Genericsynthesisscriptforsub-modules*/#/*/#/*Definedesignname*/setactive_designtap_bypass#/*/#/*DefineentryinVerilogformat*/analyzeformatverilogformat“%s%s”$active_desi

29、gn“.v”elaborate$active_designcurrent_design$active_designlink#/*/#/*Defineenvironment*/set_wire_loadSMALLmodetopset_operating_conditionsWORSTExample-dc_script.tclcont.#/*Compilewithscaninsertion*/set_fix_multiple_port_netsbuffer_constantallcompilescancheck_testcreate_test_patternssample10preview_sca

30、ninsert_scancheck_test#/*Clean-up and generate the netlist in verilog and dbformats*/remove_unconnected_portsfind-hierarchycell“*”change_nameshrulesBROGset_dont_touchcurrent_designwritehierarchyoutputformat“%s%s”$active_design“.db”write format verilog hierarchy-output format“%s%s”$active_design“.v”C

31、heckListoftheReportnIsthereanyWarningorErrormessageinlogfile?nIsthereanytimingviolation?nIsthereanydesignviolation?nIsthereanyportdirectlyconnectingtopowersuppliesinsteadofthrougha“tie1/0cell”?OutlinesLogicSynthesis&CompilingStrategyPhysicalSynthesis&CompilingStrategySynthesisUsingSynopsyssDesignCom

32、piler(DC)StaticTimingAnalysis(STA)STAUsingSynopsyssPrimetime(PT)StatisticalStaticTimingAnalysis(SSTA)HowSTAWork?AdvancedAnalysisDynamicsimulationreliesonqualityandcoverageoftest-bench,testvectorsSTAismainlyforverifyingallpossiblepathsofgate-leveldesignfortimingStaticTimingAnalysisTechniqueStaticTimi

33、ngAnalysisnInputvectorpatternindependentnEverysourceofdatalaunchischeckedatdestinationsorsinksnDeterminestheworstpossibletimeaneventwilloccurAdvantageComprehensive,guaranteealltimingpathsareanalyzedDisadvantageHowdoesdistinguishbetweenfunctional&non-functionalpathsWhatSTAtoAnalyze?Traverseallstatict

34、imingpathsnPathsbeginatsourcepinsnPrimaryInputsnPathsendatsinkpinsnPrimaryOutputsnWherevertimingcheckareperformednStorageelements(flip-flop,latch)nTimingelements(clockgate)WhatSTAtoAnalyze?cont.CalculatelatestandearliestpossibleswitchingtimesindesignDeterminethearrivaltimeofsignalsfortheworstcase(la

35、testorearliest)ofallpossiblepathsComparecalculatedsignalarrivaltimeswithexpectedtimesat“endpoints”IttypicallyReports:nSetup/holdtimenClockskewnMaximumtransitionnMaximumfanoutnMaximumcapacitancenMaximumtransitionnWhatSTAnottoAnalyze?ItdoesnotperformadelayanalysisbasedfunctionalsimulationItdoesnotcons

36、iderthelogicfunctioningofthecircuitsItdoesnotsupportself-timedasynchronouslogicwherenoglobalclockisusedTypeofTimingPathExampleFromprimaryinputstoflip-flopsFromflip-floptoflip-flopFromflip-floptoprimaryoutputFromprimaryinputstoprimaryoutputSomeBasicConceptsSetupTimeandHoldTimeforFFsSetup Time-The len

37、gth of time that data must stabilize before the clock transition.Hold Time-The length of time that data must remain stable at the input pin after the active clock transitionRecoveryTimeRecoverytime-istheminimumlengthoftimethattheactivelowsetorresetsignalmustremainhighbeforetheactiveedgeoftheclocktoe

38、nsurecorrectfunctioningofthecell.TimeSlackSlacksisusedtodescribehowmuchofthebudgetdidthelogicusedupSlack-theresultingmarginbetweenrequired&actualtimeofsignaltravelinginthepath.nPositiveslackorzeromeansmeetconstraintsnNegativeslackmeansviolateconstraintSpeedvs.SlackTheworstcaselogicpathdeterminethema

39、ximumspeed(minimumclockperiod)forasynchronoussystemExample:clockperiod=10nsPowervs.SlackLargepositiveslacknLargesizenLargepowerWhatistheideaslack?CheckTimingViolationsLongpathanalysisnVerifysignalsdontarrivetoolatenIdentifythespeedofthesystemnReport“setup-time”violationMoresetup-timeviolationshappen

40、inworst,slow,PVT(ProcessVoltageTemperature)conditionnTip:Checksetup-timeviolationusingtheworstPVTlibCheckTimingViolationscont.ShortpathanalysisnVerifysignalsdontarrivetooearlynIdentifypotentialracehazardsinadesignnReportas“hold-time”violationMorehold-timeviolationhappeninbest(fast)PVTnTip:checkhold-

41、timeviolationusingthebestPVTlibHowtofixthetimingviolation?nSetuptimenHoldtimeMethodstoFixTimingViolationTofixsetuptimingviolation:1.Re-synthesisthedesignwithoverconstraint,targetingtheviolationpathforfurtheroptimization2.DoECOwithoutre-synthesis3.Changethestructure,re-writeRTLTofixtheholdtimeviolati

42、on:1.Addingbuffers2.MostofP&Rtoolshave“fixhold”optionWhatamIgoingtodowiththeasynchronouslogic?nYoucanisolatethistypeoflogicinalevelofhierarchy,setfalsepath,thenusefull-timinggate-levelsimulationtoverifyvalidtimingandfunctionality.OutlinesLogicSynthesis&CompilingStrategyPhysicalSynthesis&CompilingStr

43、ategySynthesisUsingSynopsyssDesignCompiler(DC)StaticTimingAnalysis(STA)STAUsingSynopsyssPrimetime(PT)StatisticalStaticTimingAnalysis(SSTA)Flow of STA with Synopsyss PTSTAwithPrimetime(PT)IncontrastwithDCsinternalSTAengine,PTisfaster,takeuplessmemory,hasadditionalfeatureBasicsetupandconstraintsinSyno

44、psyssDCcanbeusedforPTRun PTSuggest to have 3 files:Startup fileSame as that used for DC:.synopsys_dc.setupAware operating conditionConstraint filesSimilar as that used for DC:constraints.tclDifferences:clock definition Pre-layout and Post-layoutPT scriptspt_script.tclRead net RC from back annotation

45、 in formats of SDF,SPEF,RSPF,DSPF ClockDefinitionforPre-layoutPre-layout(beforeclktreesynthesis)Create_clockperiod40waveform020CLKSet_clock_latencysource0.2CLKSet_clock_uncertainty-setup0.5-hold0.5CLKSet_dont_touch_networkCLKSet_ideal_networkCLKSet_dont_touch_networkpreventtoaddbuffertreeonclknetwor

46、kSet_ideal_networkpreventDRCreport(e.g,transition,fanout,cap)onclocknetworkClockDefinitionforPost-layoutPost-layouthaveclktreeinsertioninthenetlistCreate_clockperiod40waveform020CLKSet_clock_latencysource0.2CLKSet_propagated_clockCLKRemoveset_clock_uncertaintyoptionIncludeofset_propagated_clockoptio

47、nRemoveset_clock_transitioncommandKeepset_clock_latency(asclocksourcejitter)toensurearobustdesignforawiderprocessvarianceAnalyzingReportReport_timingdelay_maxforchecksetuptimingviolation(defaultsettingbyPT)Report_timingdelay_minforcheckholdtimingviolationReport_constraintall-violatorsIsthereanyWarni

48、ngorErrormessageinlogfile?nWhatwillhappenifnoclkisdefinedforsomeFFs?OutlinesLogicSynthesis&CompilingStrategyinSoCDesignPhysicalSynthesis&CompilingStrategyinSoCDesignSynthesisUsingSynopsyssDesignCompiler(DC)StaticTimingAnalysis(STA)STAUsingSynopsyssPrimetime(PT)StatisticalStaticTimingAnalysis(SSTA)Pr

49、ocessVariationsProcessvariationsnChannelwidth,lengthnOxidethicknessnDielectricconstantnInterconnectwirewidthandlengthThepercentageofthevariationversusabsolutevalueforparametersn2030%intodaystechnologynLargerinthefutureSource:“Models of process variations in device and interconnect”Duane Boning,MIT&S

50、ani Nassif,IBM ARL.EnvironmentVariationsTemperaturevariationSupplyvoltagevariationCross-talknoiseConventionalmethodtodealwiththevariationsanduncertaintiesistodesignthecircuitthatguaranteethefunctionalityintheworst-casecornerWorstCaseTimingAnalysisExample:LongestpathDelayof16-bitAddernMonteCarlon3=1.