【精品】VHDL双语教学第11章精品ppt课件.ppt

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1、VHDL双语教学第11章Balance of Signal DelayOptimize of Late Arrived SignalLate Arrived SignalLate Arrived SignalMultiple IF StatementLate Arrived SignalPriority Encoded IF For Late Arrived Control SignalLate Arrived Control SignalA(1)A(2)A(3)A(4)A(5)A(6)zC(1)C(2)C(3)C(4)C(5)Late Arrived Control Signal(Impro

2、vement)A(1)A(2)A(3)A(4)A(5)A(6)z1C(1)C(2)C(3)C(5)C(4)A(4)z1zImproved CodeLate Arrived Signal in CASE Statement(contd.)Improved Code(Schematic)VHDL Code Before Optimize(Case-When Clasue)VHDL Code After Optimize(Case-When Clasue)Merge both the C condition and the sel conditionDelay in CASE Statement(S

3、chematic)Sel(0)Sel(1)Sel(2)ZDelay in CASE Statement(Improvement)Sel(0)0Sel(2)1Sel(1)Z1Z2ZDelay in CASE StatementSel(1)is slowSel(1)=1Sel(1)=0Improved CodeClose to final outputLong Calculation Path Long Calculation Path(Schematic)Improved CodeImproved Code(Schematic)Decoder Using IndexingIn1_int as i

4、ndexI is index,in1_int is compared in loop.Out1(i)is accessed by variable iDecoder Using LoopDecoder Using Indexing vs.LoopMultiple Inputs XOR GateXOR Chains(Schematic)XOR TreeXOR Tree(Schematic)Multiplex ChainMultiplex Chain(Schematic)Multiplex TreeOperator in Conditional Expression SchematicImprov

5、ed CodeImproved Code(Schematic)Unintentional LatchData_in Data_outCond_1 Unnecessary Calculation in LOOPCoding Style For Synthesis(1)Omit wait for XX ns;Omit(Q=0 after XX ns)Using shifter register insteadD QD QD QCoding Style For Synthesis(2)Omit Initial Valuesvariable SUM:INTEGER:=0;Using power on

6、set/reset signal insteadD QRSCoding Style For Synthesis(3)Do not use variables for constantsUse constCoding Style For Synthesis(4)Indenting Your Codes Coding Style For Synthesis(5)Use std_logic9 valueAutomatically initialized to an unknown valueEasy to perform a board-level simulationCoding Style For Synthesis(6)Do not use buffers