数字集成电路分析与设计 (11).ppt

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1、The Wire2The Wire1.Introduction2.Capacitance3.Resistance4.Electrical Wire Models5.Summary6.Textbook ReferenceChapter Outline31.Introduction:Three Major Interconnection LayersThree Major Interconnection LayersLayers used to realize interconnection in state-of the-art MOS ICUpper layer:multiple layers

2、 of aluminum or copperMiddle layer:at least one layer of polysiliconLower layer:heavily doped n+or p+diffusion layer,which is typically used for the realization of source and drain regions.The Wire41.Introduction:Wire Examples0.35 um High End Microprocessor0.1 um High End MicroprocessorThe Wire51.In

3、troduction:The WireSchematic ViewPhysical viewTransmittersReceiverThese wires belong to the same layerSchematic and physical views of wiring of bus networkThe Wire61.Introduction:Wire ModelsAll-inclusive ModelCapacitance only models Wire models for the circuit of previous foilThe Wire71.Introduction

4、:Interconnect ParasiticsInterconnect parasiticsCause an increase in propagation delay,or,equivalently,a drop in performanceHave an impact on the energy dissipation and the power distributionCause the introduction of extra noise sources,which affect the reliability of the circuitClasses of parasitics

5、CapacitiveResistiveInductiveThe Wire8Chapter Outline1.Introduction2.Capacitance3.Resistance4.Electrical Wire Models5.Summary6.Textbook ReferenceThe Wire9VDDVinVoutM1VDDVout2M2M3M4Cdb2Cdb1Cgd12CwCg3Cg4CL Parasitic capacitance CL of the cascaded inverter pairInterconnect2.Capacitance:Capacitance of Wi

6、re InterconnectCapacitance of Wire InterconnectSimplified ModelDriverFan-outThe Wire10 Parallel-plate（W tox）toxHLWSiO2substrateElectric fieldW、tox1/S Scaling behaviorL 1/SL2.Capacitance:Capacitance Model Current flowParallel-plate capacitance model of interconnect wire Exploiting parallel-plate Cap.

7、model,the wire Cap.can be expressed as:u tox and eox stand for the thickness and permitivity of the dielectric layer.The Wire11 Permittivity:e eox=e ere e02.Capacitance:Capacitance Model The Wire12Intel 0.25um interconnect With device dimensions scaling downTo minimize the resistance of the wires,it

8、 is desirable to keep the cross section(W x H)of the wire as large as possibleSmall value of W leads to denser wiring and less area overheadWitnessing a steady reduction in the W/H ratio(even below unity)Fringing Cap.FringingP-PFringingP-PFringingInter-wireP-P2.Capacitance:Fringing CapacitanceThe Wi

9、re132.Capacitance:Fringing CapacitanceIntel 0.18um interconnectH WThe Wire14(a)Fringing fields(b)Model of fringing-field capacitance This model decomposes the Cap.into two parts:parallel-plate Cap.and fringing Cap.Caps.of interconnect wire as a function of W/tdi,including fringing-field effects.Ctot

10、al2.Capacitance:Fringing CapacitanceThe WireCparallel-plate152.Capacitance:Wiring Capacitances(0.25 mm CMOS)Wiring Capacitances(0.25 mm CMOS)FieldActivePolyAL1AL2AL3AL4AL5Poly8854AL1304157404754AL21315173625272945AL38.99.41015411819202749AL46.56.87.08.91535141515182745AL55.25.45.46.69.11438121212141

11、92752Red：upper layerBlue：Lower layerShadowless:P-P Cap.(aF/um2)Shadowed :fringing Cap.(aF/um)both sides should be consideredThe Wire162.Capacitance:Example of Wire Capacitance CalculationExample of Wire Capacitance CalculationlExample:Aluminum wire with L10cm,W1um,calculate its total capacitance.P-P

12、 Cap.:Fringing Cap.:Total Cap.:C groundThe Wire17LayerCap.FringingInterwireP-PGround 2.Capacitance:Interwire CapacitanceInter wire Cap.(Unit:aF/um)Capacitive coupling between wiresW/HThe Wire18Example:Aluminum wire with L10cm,W1um,calculate its total capacitance.2.Capacitance:Example of Wire Capacit

13、ance CalculationExample of Wire Capacitance CalculationP-P Cap.:Fringing Cap.:Total Cap.:The interwire Cap.(9.5pF)is almost as large as the total Cap.to ground.Interwire Cap.:Suppose that a second wire is routed along side the first one,separated by only the minimum allowed distance,calculate the in

14、terwire capacitance.C groundC adjacentThe Wire192.Capacitance:Total Capacitance Multi-Layer Cap.ModelUpper bound of total Cap.The WireCgnd=Cbot+CtopCtotal=Cgnd+2Cadj=Cbot+Ctop+2Cadj20Chapter Outline1.Introduction2.Capacitance3.Resistance4.Electrical Wire Models5.Summary6.Textbook ReferenceThe Wire21

15、3.Resistance:Resistivity and Sheet ResistanceResistivity and Sheet Resistance Model of wire resistanceWHL Sheet resistance:R(H is a constant for a given tech)：Unit:/Resistivity of commonly used conductors(at 20 oC)Resistance of a wireCurrentLWLW CurrentThe Wire223.Resistance:Modern InterconnectModer

16、n InterconnectMicrophotograph of interconnect after removal of insulatorThe Wire233.Resistance:Resistivity and Sheet ResistanceResistivity and Sheet ResistanceSheet ResistanceThe Wire24 Polycide Gate MOSFETn+n+SiO2PolySiliconSilicidepSilicides:WSi2,TiSi2,PtSi2 and TaSiConductivity:8-10 times better

17、than PolySilicon3.Resistance:Dealing with ResistanceThe Wire253.Resistance:Resistivity and Sheet ResistanceResistivity and Sheet ResistanceSheet ResistanceThe Wire26Selective Technology ScalingScaling down W and L,but keep H a constantMore Interconnect Layersreduce average wire-lengthUse Better Inte

18、rconnect Materialse.g.copper,silicides3.Resistance:Dealing with ResistanceThe Wire27Chapter Outline1.Introduction2.Capacitance3.Resistance4.Electrical Wire Models5.Summary6.Textbook ReferenceThe Wire284.Electrical Wire Model:IntroductionThe Ideal WireLumped Model Lumped C Model Lumped RC ModelDistri

19、buted rc-LineTransmission LineWires occur as simple lines with no attached parameters or parasiticsThe Wire29 When only a single parasitic component is dominant,or when the interaction between the components is small,or when looking at only one aspect of the circuit behavior,it is often useful to lu

20、mp the different fractions into a single circuit element.Lumped ModelClumpedL CwireCwire:Cap.per unit lengthDriver:“Voltage Source”+“Source Resistance”VoutDrivercwireLumped C Model4.Electrical Wire Model:Lumped Model(Lumped RC Model)Lumped Model(Lumped RC Model)The Wire30 Tree-structured RC network(

21、RC tree)Features of RC treeu Possess a single input nodeu All capacitors are between a node and groundu Contain no resistive loopsu Path Resistance Rii:total resistance along the unique resistive path between the source node r and any node i of the network.i.e.R44R1+R3+R4 Definition Lump the total w

22、ire resistance of each wire segment into one single R,and similarly combines the global capacitance into a single capacitor C.Lumped RC model4.Electrical Wire Model:Lumped Model(Lumped RC Model)Lumped Model(Lumped RC Model)The Wire31i.e.:Ri4R1+R3，Ri2R1Shared Path Resistance Rik:the resistance shared

23、 among the paths from the root node r to nodes k and i Definition:4.Electrical Wire Model:Lumped Model(Lumped RC Model)Lumped Model(Lumped RC Model)The Wire32 Assume now that each of the N nodes of the network is initially discharged to GND,and that a step input is applied at node r at time t=0,the

24、elmore delay at node i is given by:Example:compute the elmore delay of node i in the above RC tree network Elmore Delay4.Electrical Wire Model:Lumped Model(Lumped RC Model)Lumped Model(Lumped RC Model)The Wire33 A simple nonbranched RC chain(or ladder)Shared Path Resistance Path Resistance Elmore de

25、lay:R1VinVNii-1R2C1C212Ri-1RiRNCi-1CiCNu From Vin to node N：u From Vin to node i：4.Electrical Wire Model:Lumped Model(Lumped RC Model)Lumped Model(Lumped RC Model)The Wire34l Assume all NMOS transistors have an equal size：tpHL=0.69R(C1+2C2+3C3+4CL)4-Input NAND Gatel Each capacitor will be discharged

26、 through the resistors,thus delay can be computed as:tpHL=0.69 R1C1+(R1+R2)C2 +(R1+R2+R3)C3 +(R1+R2+R3+R4)CL tpHL is a quadratic function of fan-in(because the pull-down resistance and the load capacitance are increased simultaneously with fan-in)tpLH is a linear function of fan-in(because only load

27、 capacitance is increased with fan-in)Progressive transistor scaling:M1 M2 M3 M42.Static CMOS Design:Complementary CMOS(Fan-in Consideration)DCBADCBACLC3C2C1M1M2M3M4M5M6M7M8The Wire35 Assume r and c are resistance and capacitance per unit length,therefore the resistance of capacitance of each segmen

28、t are given by rL/N and cL/N4.Electrical Wire Model:Lumped Model(Lumped RC Model)Lumped Model(Lumped RC Model)Example:the wire with a total length of L is partitioned into N identical segments,each with a length of L/N Exploiting Elmore delay method,the delay can be expressed as:u R=rL and C=cL are

29、lumped resistance and capacitance of the wire respectively For very large values of N,this model asymptotically approaches the distributed rc lineuDelay of a wire is a quadratic function of its lengthuDelay of the distributed rc line is one half of the delay that would have been predicted by the lum

30、ped RC model.The Wire36Vout(r,c,L)VinSchematic symbol of distributed rc lineDistributed rc ModelrLVinVoutc LrLrLrLrLc Lc Lc Lc LVi-1Vi+1ViLr,c:resistance and capacitance per unit length4.Electrical Wire Model:Distributed rc LineThe Wire37 Voltage at node i is determined by the following partial diff

31、erential equations:Distributed rc ModelrLVinVoutc LrLrLrLrLc Lc Lc Lc LVi-1Vi+1ViLIi-1,iIiIi+1,i4.Electrical Wire Model:Distributed rc LineThe Wire38Diffusion Equation V is the voltage at a particular point in the wire,x is the distance between this point and the signal sourceu No closed-form soluti

32、on exists for this equation4.Electrical Wire Model:Distributed rc LineThe Wire39Simulated step response of the resistive-capacitance wire as a function of time and place00.511.522.533.544.5500.511.522.5Time(ns)Voltage (V)x=L/10 x=L/4 x=L/2 x=L 4.Electrical Wire Model:Distributed rc LineThe Wire40Vol

33、tage RangeLumped RC NetworkDistributed rc Network050%(tp)0.69RC0.38RC063%()RC0.5RC10%90%(tr)2.2RC0.9RC4.Electrical Wire Model:Distributed rc LineThe Wire41Design Rules of Thumbrc delays should only be considered when tprc tpgate of the driving gaterc delays should only be considered when the rise(fa

34、ll)time at the line input is smaller than RC,the rise(fall)time of the line trise RCwhen not met,the change in the signal is slower than the propagation delay of the wireR and C are lumped resistance and capacitance of the wire respectively4.Electrical Wire Model:Distributed rc LineThe Wire42Exploit

35、ing the first design rule of the previous foil,if RsCW (RWCW)/2,distributed rc line should be adopted to calculate the delay Derive the propagation delay:r and c represent the resistance and Cap.per unit length between node and ground.，Vout4.Electrical Wire Model:Distributed rc LineThe Wire434.Elect

36、rical Wire Model:Distributed rc Linen Problem:Calculate the propagation delay from A to B A The driver is represented by Rdr,which is the average of Reqn and Reqp Cint accounts for the intrinsic capacitance of the driver Cfanout accounts for the input capacitance of the fanout gateBRdrFigure 5-24 Pa

37、ge 213 The Wire44 RC/2C/2TR/2CR/2 2R/2C/2R/2C/4C/4 3R/3C/3R/3C/6C/6C/3R/3T2R/2C/2R/4R/4C/2T3R/3C/3R/3R/6C/3C/3R/64.Electrical Wire Model:Spice ModelThe Wire45Chapter Outline1.Introduction2.Capacitance3.Resistance4.Electrical Wire Models5.Summary6.Textbook ReferenceThe Wire465.SummaryCapacitance of t

38、he wireResistance of the wireWire ModelLumped RC modelDistributed rc modelThe Wire476.Textbook Reference4.1 Introduction4.2 A First Glance4.3 Interconnect parameters4.3.1 Capacitance4.3.2 Resistance4.4 Electrical Wire Model4.4.1 The Ideal Wire4.4.2 The lumped Model4.4.3 The lumped RC Model4.4.4 The distributed rc line4.5 SPICE Wire ModelThe Wire