数字集成电路分析与设计 (2).ppt

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1、32Introduction and Implementation Strategies for Digital IC“Hard”Macro Modules25632(or 8192 bit)SRAMGenerated by hard-macro module generator4.Semicustom Design Methodology:MacroCells33Introduction and Implementation Strategies for Digital ICA Protocol Processor for Wireless:an example of a hybrid AS

2、IC design methodology.4.Semicustom Design Methodology:MacroCellsIntroduction and Implementation Strategies for Digital ICArchitecture of Node SoCDie Photo(Wireless Image Sensor Node IJE 2013)344.Semicustom Design Methodology:System-On-a-Chipa35Introduction and Implementation Strategies for Digital I

3、CHDLLogic SynthesisFloorplanningPlacementRoutingTape-outCircuit ExtractionPre-Layout SimulationPost-Layout SimulationStructuralStructuralPhysicalPhysicalBehavioralBehavioralDesign CaptureDesign IterationDesign Iteration4.Semicustom Design Methodology:Cell-based Design FlowCell-based Semicustom Desig

4、n Flow36Introduction and Implementation Strategies for Digital ICThe“Design Closure”ProblemIterative Removal of Timing Violations(white lines)Initial DesignIntermediate designFinal design4.Semicustom Design Methodology:Cell-based Design Flow67Introduction and Implementation Strategies for Digital IC

5、4.Semicustom Design Methodology:Cell-based Design FlownWhy are the cell-based semicustom approaches so popular?lThe emergence of mature logic&physical synthesis EDA toolslThe advancements of the automatic place&route EDA tools38Introduction and Implementation Strategies for Digital ICIntegrating Syn

6、thesis with Physical DesignPhysical SynthesisRTL(Timing)ConstraintsPlace-and-RouteOptimizationArtworkNetlist with Place-and-Route InfoMacromodulesFixed netlists4.Semicustom Design Methodology:Cell-based Design Flow39Introduction and Implementation Strategies for Digital ICSRAMSRAMSRAMSRAMProgram Log

7、ic Standard Cell Macrocell（Hard MacroModule）Microphotograph of Jpeg2000 JSSC 2004Logical&Physical Synthesis+Automatic Place&Routing4.Semicustom Design Methodology:Cell-based Design Example40Introduction and Implementation Strategies for Digital ICSeldom used now!CustomStandard CellsCompiled CellsMac

8、ro CellsCell-basedPre-diffused(Gate Arrays)Pre-wired(FPGAs)Array-basedSemicustomDigital Circuit Implementation Approaches4.Semicustom Design Methodology41Introduction and Implementation Strategies for Digital ICnBased on Memory technologylFuse-based(program-once)(seldom used)lNon-volatile EPROM base

9、d(often used)lRAM based(most often used)nProgrammable Logic StylelArray-Based(often used)lMux-Based(most often used)lLook-up Table(most often used)nProgrammable Interconnect StylelChannel-routing(often used)lMesh networks(most often used)Classification of pre-wired arrays(or field-programmable devic

10、es)4.Semicustom Design Methodology:Pre-wired Arrays42Introduction and Implementation Strategies for Digital ICnBased on Memory technologylFuse-based(program-once)(seldom used)lNon-volatile EPROM based(often used)lRAM based(most often used)nProgrammable Logic StylelArray-Based(often used)lMux-Based(m

11、ost often used)lLook-up Table(most often used)nProgrammable Interconnect StylelChannel-routing(often used)lMesh networks(most often used)Classification of pre-wired arrays(or field-programmable devices)4.Semicustom Design Methodology:Pre-wired Arrays43Introduction and Implementation Strategies for D

12、igital ICExample Fuse-Based FPGAantifuse polysiliconONO dielectricn+antifuse diffusionOpen by default,closed by applying current pulsen Fuse-based(program-once)(seldom used)4.Semicustom Design Methodology:Memory Technology44Introduction and Implementation Strategies for Digital ICnBased on Memory te

13、chnologylFuse-based(program-once)(seldom used)lNon-volatile EPROM based(often used)lRAM based(most often used)nProgrammable Logic StylelArray-Based(often used)lMux-Based(most often used)lLook-up Table(most often used)nProgrammable Interconnect StylelChannel-routing(often used)lMesh networks(most oft

14、en used)Classification of pre-wired arrays(or field-programmable devices)4.Semicustom Design Methodology:Pre-wired ArraysArray-Based Programmable Logic45Introduction and Implementation Strategies for Digital ICPLAPROMPALI5I4O0I3I2I1I0O1O2O3Programmable AND arrayProgrammableOR arrayI5I4O0I3I2I1I0O1O2

15、O3Programmable AND arrayFixed OR arrayO0I3I2I1I0O1O2O3Fixed AND arrayProgrammableOR arrayIndicates programmable connectionIndicates fixed connection4.Semicustom Design Methodology:Programmable Logic Stylef01X2X1X0f1NANA:programmed nodeExample of Programming a PROM46Introduction and Implementation St

16、rategies for Digital ICFixed AND array4.Semicustom Design Methodology:Programmable Logic Style47Introduction and Implementation Strategies for Digital ICFA0BS12-input MUX as programmable logic blockABSF=00000X1X0Y1Y0YXXYX0YY0XY1XX Y10X10Y1111XYXYXYConfiguration4.Semicustom Design Methodology:Program

17、mable Logic StyleLook-up Table Based Logic Cell48Introduction and Implementation Strategies for Digital IC4.Semicustom Design Methodology:Programmable Logic StyleCLB of Xilinx4000 Series(Implementation example of LUT)49Introduction and Implementation Strategies for Digital ICD4C1.C4KClockD3D2D1F4F3F

18、2F1LogicfunctionofD1-D4LogicfunctionLogicfunctionofF1-F4H14Din/H2 SR/H0 ECHPBitscontrolBitscontrolMultiplexer Controlledby Configuration ProgramDy11ECQSDYQBypassxXQBypassRDDECQSDRD4-inputs LUT4.Semicustom Design Methodology:Programmable Logic StylenBased on Memory technologylFuse-based(program-once)

19、(seldom used)lNon-volatile EPROM based(often used)lRAM based(most often used)nProgrammable Logic StylelArray-Based(often used)lMux-Based(most often used)lLook-up Table(most often used)nProgrammable Interconnect StylelChannel-routing(often used)lMesh networks(most often used)50Introduction and Implem

20、entation Strategies for Digital ICClassification of pre-wired arrays(or field-programmable devices)4.Semicustom Design Methodology:Pre-wired ArraysArray-Based Programmable WiringMost often used in small-scale FPGA51Introduction and Implementation Strategies for Digital ICInput/output pinProgrammed i

21、nterconnectionInterconnectPointHorizontal tracksVertical tracksCellFuse or Antifuse can be used to replace the pass transistor4.Semicustom Design Methodology:Programmable Interconnect StyleMesh-based Interconnect NetworkOften used in medium-or large-scale FPGA52Introduction and Implementation Strate

22、gies for Digital ICSwitch BoxConnect Box4.Semicustom Design Methodology:Programmable Interconnect StyleTransistor Implementation of Mesh53Introduction and Implementation Strategies for Digital ICLUTLUTLUTLUTLUTLUT4.Semicustom Design Methodology:Programmable Interconnect StyleFPGA54Introduction and I

23、mplementation Strategies for Digital ICApplication of Xilinx VirtexII XC2V4000n RAM based n LUT basedn Mesh based 4.Semicustom Design Methodology:Application example of FPGAnIf design automation solves all our design problems,why should we be concerned with digital circuit design?lDesigning and impl

24、ementing the module librarieslCreating an adequate model of a cell or module requires an in-depth understanding of the its internal operationlThe library-based approach works fine when the design constraints are not stringentlAbstraction-based approach is only correct to a certain degreelScaling ten

25、ds to emphasize some other deficiencies of the abstraction-based modellNew design issues and constraints tend to emerge over timelTroubleshooting a design requires circuit expertise55Introduction and Implementation Strategies for Digital IC4.Semicustom Design Methodology1.Introduction to Digital IC2

26、.Architecture of Digital Processor3.Full Custom Design Methodology4.Semicustom Design Methodology5.Quality Metric of Digital IC6.Summary7.Textbook Reference56Introduction and Implementation Strategies for Digital ICChapter OutlinenHow to evaluate quality of a digital circuit(gate,block )?lPerformanc

27、elPower dissipationlEnergy consumption to perform a functionlCostlRobustnesslFunctionality57Introduction and Implementation Strategies for Digital IC5.Quality Metric of Digital IC58Introduction and Implementation Strategies for Digital IC Y Yo ou ur r c ce el ll l p ph ho on ne e h ha as s mmo or re

28、 e c co ommp pu ut ti in ng g p po ow we er r t th ha an n a al ll l o of f N NA AS SA A i in n 1 19 96 69 9.N NA AS SA A l la au un nc ch he ed d a a mma an n t to o t th he e mmo oo on n.WWe e l la au un nc ch he ed d a a b bi ir rd d i in nt to o p pi ig gs s.”G Ge eo or rg ge e B Br ra ay yiPhon

29、e 6 Plus5.Quality Metric of Digital ICnNRE(Non-Recurrent Engineering)costs(fixed cost)lDesign time and effort,Manpower,Mask generationlIndependent of the sales volumelStrongly influenced by complexity of the design,aggressiveness of the specifications,and the productivity of the designernRecurrent c

30、osts(variable cost)lSilicon processing,packaging,testlDirectly attributable to a manufactured products.lProportional to volumelProportional to chip area59Introduction and Implementation Strategies for Digital IC5.Quality Metric of Digital IC:Cost60Introduction and Implementation Strategies for Digit

31、al IC5.Quality Metric of Digital IC:Cost65nm65nm2.5-3B$2.5-3B$45nm45nm3.5-5B$3.5-5B$32nm32nm5-7B$5-7B$22nm22nm8-10B$8-10B$16nm16nm12-15B$12-15B$301Introduction and Implementation Strategies for Digital IC5.Quality Metric of Digital IC:Cost62Introduction and Implementation Strategies for Digital ICBo

32、nding wire:Die to substrateDieCavityPin:Substrate to board5.Quality Metric of Digital IC:CostSingle die63Introduction and Implementation Strategies for Digital ICWafer Going up to 12”(30cm)5.Quality Metric of Digital IC:CostDefects64Introduction and Implementation Strategies for Digital ICa is appro

33、ximately 3 5.Quality Metric of Digital IC:Cost65Introduction and Implementation Strategies for Digital ICChipMetal layersLine widthWafer costDef./cm2Area mm2Dies/waferYieldDie cost386DX20.90$9001.04336071%$4486 DX230.80$12001.08118154%$12Power PC 60140.80$17001.312111528%$53HP PA 710030.80$13001.019

34、66627%$73DEC Alpha30.70$15001.22345319%$149Super Sparc30.70$17001.62564813%$272Pentium30.80$15001.5296409%$4175.Quality Metric of Digital IC:Costn Example Dies per waferlWafer Diameter=12 inch=30 cmlDie size=2.5 cm2 66Introduction and Implementation Strategies for Digital ICNumber of dies=296-44=252

35、 15%of area not used!5.Quality Metric of Digital IC:Costn Example-YieldlWafer Diameter=12 inch=30 cmlDie size=2.5 cm2 lDefect density=1 def/cm2la=3lNumber of dies=296-44=252lYield=16%!67Introduction and Implementation Strategies for Digital ICNumber of good dies=252 x 16%=405.Quality Metric of Digit

36、al IC:CostInverters DC Operation(Voltage Transfer Characteristic)68Introduction and Implementation Strategies for Digital ICVM=f(VM)VOH=f(VOL)VOL=f(VOH)The function of a logic gate can be expressed by its VTC.V(x)V(y)VOHVOLVM fV(y)=V(x)Switching ThresholdNominal Voltage LevelsVOLVOH5.Quality Metric

37、of Digital IC:VTCMapping between analog and digital signals69Introduction and Implementation Strategies for Digital ICSlope=-1Slope=-1“0”VOLVILVIHVOHUndefinedRegion“1”VOHVOLVILVIHVINVOUT5.Quality Metric of Digital IC:VTCDefinition of Noise Margins70Introduction and Implementation Strategies for Digi

38、tal ICNoise margin highNoise margin lowVIH VILUndefinedRegion10VOH VOLNMHNMLGate OutputGate InputNML=VIL VOLNMH=VOH VIH5.Quality Metric of Digital IC:Noise MarginnTwo types of noise sources:l Noise sources proportional to the signal swing Vsw,with impact g Vsw,g stands for the gain factorl Fixed noi

39、se sources with impact f VNf,f stands for the transfer function from noise to signal node and Vf represents the amplitude of the noise source71Introduction and Implementation Strategies for Digital ICnSuppose the noise margin is half the signal swing.nFor correct operation,the impact of noise on a n

40、ode should be smaller than the noise margin5.Quality Metric of Digital IC:Noise MarginnAbsolute noise margin values are deceptivela floating node is more easily disturbed than a node driven by a low impedance(in terms of voltage)nNoise immunity is the more important metriclNoise immunity describes t

41、he capability of the circuit to suppress or reject eventual noise sourcesnA circuit with a low noise margin but with excellent noise rejection capabilities can be very robustnImportant metric of noise immunitylNoise transfer functionslOutput impedance of the driverlInput impedance of the receiver72I

42、ntroduction and Implementation Strategies for Digital IC5.Quality Metric of Digital IC:Noise ImmunityRegenerative Property73Introduction and Implementation Strategies for Digital IC A chain of invertersv0v1v2v3v4v5v6 Simulated responseRegenerative property ensures that a disturbed signal gradually c

43、onverges back to one of the nominal voltage levels after passing through a number of logical stages5.Quality Metric of Digital IC:RegenerationRegenerative Property74Introduction and Implementation Strategies for Digital ICRegenerativeNon-RegenerativeTo be regenerative,the gain of the transient regio

44、n should be larger than 1 in absolute value5.Quality Metric of Digital IC:RegenerationnRegeneration:a signal that deviates from the nominal level(VOH or VOL)gradually converges back to the nominal level after passing a chain of stages.75Introduction and Implementation Strategies for Digital IC5.Qual

45、ity Metric of Digital IC:RegenerationDefinition of Fan-in and Fan-out for digital gate76Introduction and Implementation Strategies for Digital ICNFan-out NFan-in MM5.Quality Metric of Digital IC:Fan-in&Fan-outThis is“ideality from a static point of view”77Introduction and Implementation Strategies f

46、or Digital ICRi=Ro=0g=VinVoutThe VTC of the static CMOS inverter is very close to the ideal one.5.Quality Metric of Digital IC:The Ideal Gate78Introduction and Implementation Strategies for Digital ICVout(V)VTC of NMOS Inverter,in 1970sNM =1.15VHVin(V)NM =0.21VLV =1.64VM0.01.02.03.04.05.01.02.03.04.

47、05.0V =3.5VOHV =0.45VOL5.Quality Metric of Digital IC:An Old-time InverternPropagation delaysltpHL,tpLHltp=(tpHL,tpLH)/2ldefined on 50%of the swingnRise and fall timelTime to go from 10%to 90%or vice versanPropagation is not only dependent on circuit properties but also on rise and fill times79Intro

48、duction and Implementation Strategies for Digital ICDefinition of propagation delays and rise and fall times5.Quality Metric of Digital IC:PerformancenPerformance of digital systems is often expressed in#instructions that can be executed in a period of the(MIPS or MOPS).This depends on the processor

49、-architecture,the software architecture,80Introduction and Implementation Strategies for Digital IC5.Quality Metric of Digital IC:PerformancenIn this course:focus on circuit design lCircuit performance is expressed as the rate at which the circuit can operate.It will show that this is related to the

50、 maximum clock frequency of the circuit.lThe maximum clock frequency is related to time the circuits take to calculate their outputs,i.e.the propagation delay81Introduction and Implementation Strategies for Digital ICRing oscillator circuit for propagation-delay measurement=2Ring oscillator used for