数字电路英文版第十单元.pptx

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1、KEY TERMSBidirectional Having two directions.In a bidirectional shift register,the stored data can be shifted right or left.Johnson counter A type of register in which a specified prestored pattern of 1s and 0s is shifted through the stages,creating a unique sequence of bit patterns.第1页/共66页Load To

2、enter data into a shift register.Ring counter A register in which a certain pattern of 1s and 0s is continuously recirculated.Stage One storage element in a register.第2页/共66页Shift To move binary data from state to stage within a shift register or other storage device or to move binary data into or o

3、ut of the device.Universal shift register A register that has both serial and parallel input and output capability.第3页/共66页 Shift registers consist of an arrangement of flip-flops and are important in applications involving the storage and transfer of data in a digital system.10.1 BASIC SHIFT REGIST

4、ER 10.1 BASIC SHIFT REGISTER FUNCTIONSFUNCTIONS2.第4页/共66页D0QC0CLKD1QC1CLK1 is stored0 is storedThe flip-flop as a storage element.3.第5页/共66页DatainDataoutDatainDataout(a)Serial in/shift right/serial out(b)Serial in/shift left/serial out4.第6页/共66页DatainDataout(c)Parallel in/serial outData inData out(d

5、)Serial in/parallel out5.第7页/共66页Data inDataout(e)Parallel in/parallel out(f)Rotate right(g)Rotate left6.第8页/共66页 10.2 SERIAL IN/SERIAL OUT 10.2 SERIAL IN/SERIAL OUT SHIFT REGISTERSSHIFT REGISTERS The serial in/serial out shift register accepts data serially that is,one bit at a time on a single lin

6、e.It produces the stored information on its output also in serial form.7.第9页/共66页DCDCDCDCQ0Q1Q2Q3Q3Serial data outputSerial data outputSerial data inputCLKSerial in/serial out shift register8.FF0FF1FF2FF3第10页/共66页DCDCDCDCFF0FF1FF2FF3CLKData inputRegisterinitiallyCLEAR0000Q3DCDCDCDCFF0FF1FF2FF31st da

7、taAfter CLK10000Q3bit=0CLK 19.第11页/共66页DCDCDCDCFF0FF1FF2FF32st dataAfter CLK20100Q3bit=1CLK 2DCDCDCDCFF0FF1FF2FF33st dataAfter CLK31000Q3bit=0CLK 310.第12页/共66页DCDCDCDCFF0FF1FF2FF34st dataAfter CLK40110Q3bit=1CLK 4Four bit(1010)being entered serially into the register.11.第13页/共66页DCDCDCDCFF0FF1FF2FF3

8、After CLK401100CLKregistercontains1010DCDCDCDCFF0FF1FF2FF31st dataAfter CLK51001Q3bitCLK 5Q302nd date bit 12.第14页/共66页DCDCDCDCFF0FF1FF2FF3After CLK70001CLK 70DCDCDCDCFF0FF1FF2FF3After CLK60010CLK 60Q3Q34th date bit 3rd date bit 13.第15页/共66页DCDCDCDCFF0FF1FF2FF3After CLK80000CLK 80Q3registeris CLEARFo

9、ur bit(1010)being serially shiftedout of the register and replaced by all zeros.14.第16页/共66页EXAMPLE 10-1 Q4Q3Q2Q1Q0=11010DCDCDCDCFF0FF1FF2FF3DCFF4Q0Q1Q2Q3Q4Data inputData outputCLK 15.第17页/共66页CLKData inputQ0Q1Q2Q3Q41111110000Data bitstoredafterpulseclockfive16.第18页/共66页 10.3 SERIAL IN/PARALLEL 10.3

10、 SERIAL IN/PARALLEL OUT SHIFT REGISTERSOUT SHIFT REGISTERS Data bits are entered serially into this type of register in the same manner as discussed in Section 10-2.The difference is the way in which the data bits are taken out of the register;in the parallel output register,the output of each stage

11、 is available.17.第19页/共66页Once the data are stored,each bit appears on its respective output line,and all bits are available simultaneously,rather than on a bit-by-bit basis as with the serial output.18.第20页/共66页DCDCDCDCFF0FF1FF2FF3DataCLKQ3inputQ0Q1Q2SRG 4DCQ3Q0Q1Q2Data inputCLK19.第21页/共66页EXAMPLE

12、10-2 The register contains 0110.SRG 4DCQ3Q0Q1Q2CLKQ0Q1Q2Q31111000020.第22页/共66页 10.4 PARALLEL IN/SERIAL 10.4 PARALLEL IN/SERIAL OUT SHIFT REGISTERSOUT SHIFT REGISTERS For a register with parallel data inputs,the bits are entered simultaneously into their respective stages on parallel lines rather tha

13、n on a bit-by-bit basis on one line as with serial data inputs.The serial output is the same as described in Section 10-2,once the data are completely stored in the register.21.第23页/共66页DCDCDCDCdataCLKQ3outputQ0Q1Q2SHIFT/LOADD3D0D1D2SerialG3G1G2G6G5G422.第24页/共66页SRG 4CD3D0D1D2SHIFT/LOADCLKSerial dat

14、a out(b)Logic symbol23.Data in第25页/共66页 10.5 PARALLEL IN/PARALLEL 10.5 PARALLEL IN/PARALLEL OUT SHIFT REGISTERSOUT SHIFT REGISTERS Parallel entry of data was described in Section10-4,and parallel output of data has also been discussed previously.The parallel in/parallel out register employs both met

15、hods.Immediately following the simultaneous entry of all data bits,the bits appear on the parallel outputs.24.第26页/共66页DCDCDCDCQ0Q1Q2Q3D3CLKD0D1D2Parallel data outputParallel data input25.第27页/共66页 10.6 BIDIRECTIONAL SHIFT 10.6 BIDIRECTIONAL SHIFT REGISTERSREGISTERS A bidirectional shift register is

16、 one in which the data can be shift either left or right.It can be implemented by using gating logic that enables the transfer of a data bit from one stage to the next stage to the right or to the left,depending on the level of a control line.26.第28页/共66页DCDCDCDCCLKQ3Serial data inQ0Q1Q2R/LG8G6G7G4G

17、3G2G1G527.第29页/共66页CLKQ0Q1Q2123456789Q3111111111111111100000000000000000000000(right)(right)(left)(left)0EXAMPLE 10-4 Q3Q2Q1Q0=1011R/L28.第30页/共66页 10.7 SHIFT REGISTER COUNTERS 10.7 SHIFT REGISTER COUNTERS The Johnson Counter:In a Johnson counter the complement of the output of the last flip-flop is

18、connected back to the D input of the first flip-flop.29.第31页/共66页Clock Pulse Q0 Q1 Q2 Q3 0 0 0 0 0 1 1 0 0 0 2 1 1 0 0 3 1 1 1 0 4 1 1 1 1 5 0 1 1 1 6 0 0 1 1 7 0 0 0 1Four-bit Johnson sequence.2n states30.第32页/共66页DCDCDCDCQ0Q1Q2FF1Q3FF2FF3FF0CLK(a)Four-bit Johnson counter31.第33页/共66页CLKQ0Q1Q2123456

19、78Q3Timing sequence for a 4-bit Johnson counter32.第34页/共66页 The Ring Counter:The ring counter utilizes one flip-flop for each state in its sequence.33.第35页/共66页DCDCDCDCQ0Q1Q2FF1CLRFF3PRECLKDCDCQ3Q4Q5A 6-bit ring counter 34.第36页/共66页Clock Pulse Q0 Q1 Q2 Q3 Q4 Q5 0 1 0 0 0 0 0 1 0 1 0 0 0 0 2 0 0 1 0

20、0 0 3 0 0 0 1 0 0 4 0 0 0 0 1 0 5 0 0 0 0 0 1Six-bit ring counter sequence.35.第37页/共66页CLKQ0Q1Q212345678Q3Q5Q436.第38页/共66页 10.8 SHIFT REGISTER APPLICATION 10.8 SHIFT REGISTER APPLICATIONTime DelaySRG 8ACCLKData in123456789Data outData in1 us8 usQ7Q7CLK 1MHz第39页/共66页EXAMPLE 10-6 Determine the amount

21、of time delay between the serial input and each output in Figure 10-29.Show a timing diagram to illustrate.SRG 8*ACCLK 500 kHzQ7Q0Q1Q2Q3Q4Q6Q5CLRData inB*Data shift from Q0 toward Q7第40页/共66页CLK123456789Data inQ6Q0Q1Q2Q3Q4Q5Q72 us16 us第41页/共66页第42页/共66页第43页/共66页第44页/共66页第45页/共66页第46页/共66页第47页/共66页SR

22、G 4Data BitsCQ7D0Q3+V+SH/LDSRG 87419574195D4D1D2D3D6D5D7Start bitStop bitCLKC第48页/共66页SRG 4Data BitsCQ7D0Q3+V+SH/LDSRG 87419574195D4D1D2D3D6D5D7Start bitStop bitCLKC43.See Figure as follow for one possible implementation.第49页/共66页Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 D0 D1 D2 D3 D4 D5 D6 D

23、7 74LS16474LS199SRSLS1S0CLRBACLR+5VQ0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 D0 D1 D2 D3 D4 D5 D6 D7 74LS16474LS199SRSLS1S0CLRBACLR+5VLOADENPENTCLRD3 D2 D1 D0Q3 Q2 Q1 Q074LS163JKCLRPREQRCO+5V+5V+5VParallel Data Out(HIGH)Parallel Data Out(LOW)Data In CLK 第50页/共66页Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q0 Q1 Q

24、2 Q3 Q4 Q5 Q6 Q7 D0 D1 D2 D3 D4 D5 D6 D7 74LS16474LS199SRSLS1S0CLRBACLR+5VQ0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 D0 D1 D2 D3 D4 D5 D6 D7 74LS16474LS199SRSLS1S0CLRBACLR+5VLOADENPENTCLRD3 D2 D1 D0Q3 Q2 Q1 Q074LS163JKCLRPREQRCO+5V+5V+5VParallel Data Out(HIGH)Parallel Data Out(LOW)Data In CLK 4

25、2.Portions of the circuit that require modification for 16-bit conversion.7476第51页/共66页Digital System Design with VHDLCombinational building blocks1.Decoder1.1 2 to 4 decoder第52页/共66页library ieee;use ieee.std_logic_1164.all;entity decoder is port(a:in std_ulogic_vector(1 downto 0);z:out std_ulogic_v

26、ector(3 downto 0);end entity decoder;第53页/共66页architecture when_else of decoder is begin z=“0001”when a=“00”else “0010”when a=“01”else “0100”when a=“10”else “1000”when a=“11”else “XXXX”;end architecture when_else;第54页/共66页Seven-segment displaylibrary ieee;use ieee.std_logic_1164.all;entity seven_seg

27、 is port(a:in integer range 0 to 15;z:out std_ulogic_vector(6 downto 0);end entity seven_seg;第55页/共66页architecture with_select of seven_seg is begin z=“1111110”when 0,“0110000”when 1,“1101101”when 2,“1111001”when 3,“0110011”when 4,“1011011”when 5,“1011111”when 6,第56页/共66页 “1010010”when 7,“1111111”wh

28、en 8,“1111011”when 9,“1001111”when 10 to 15;end architecture with_select;第57页/共66页Multiplexers4 to 1 multiplexerlibrary ieee;use ieee.std_logic_1164.all;entity mux is port(a,b,c,d:in std_ulogic;s:in std_ulogic_vector(1 downto 0);y:out std_ulogic);end entity mux;第58页/共66页architecture mux1 of mux is b

29、egin with s select y=a when “00”;b when “01”;c when “10”;d when “11”;“X”when others;end architecture mux1;第59页/共66页architecture mux2 of mux is begin y=a when s=“00”else;b when s=“01”else;c when s=“10”else;d when s=“11”else;“X”;end architecture mux2;第60页/共66页VHDL models of sequential logic blocks1.Fl

30、ip-flopsEdge-triggered D flip-floplibrary ieee;use ieee.std_logic_1164.all;entity D_FF is port(D,Clock:in std_ulogic;Q:out std_ulogic);end entity D_FF;第61页/共66页architecture behavioural of D_FF is begin p0:process is begin wait until(Clock=1);Q=D;end process p0;end architecture behavioural;第62页/共66页S

31、hift registerslibrary ieee;use ieee.std_logic_1164.all;entity sipo is generic(n:natural:=8);port(a:in std_ulogic;q:out std_ulogic_vector(n-1 downto 0);clk:in std_ulogic);end entity sipo;第63页/共66页architecture rtl of sipo is begin p0:process(clk)is variable reg:std_ulogic_vector(n-1 downto 0);begin if rising_edge(clk)then reg:=reg(n-2 downto 0)&a;q 0);elsif rising_edge(clk)then reg:=reg(n-2 downto 0)¬ reg(n-1);end if;q=reg;end process p0;end architecture johnson;第65页/共66页感谢您的观看！第66页/共66页