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1、SOLUTIONS MANUALCOMPUTER ORGANIZATION ANDARCHITECTUREDESIGNING FOR PERFORMANCESEVENTH EDITIONWILLIAM STALLINGSCopyright 2005:William Stallings-2-2005 by William StallingsAll rights reserved.No part of this document maybe reproduced,in any form or by any means,orposted on the Internet,without permiss

2、ion inwriting from the author.NOTICEThis manual contains solutions to all of the review questions andhomework problems in Computer Organization and Architecture,Seventh Edition.If you spot an error in a solution or in the wording of aproblem,I would greatly appreciate it if you would forward theinfo

3、rmation via email to .An errata sheet for this manual,if needed,is available at WilliamSW.S.-4-TABLE OF CONTENTSChapter 2:Computer Evolution and Performance.5Chapter 3:Computer Function and Interconnection.9Chapter 4:Cache Memory.14Chapter 5:Internal Memory.27Chapter 6:External Memory.33Chapter 7:In

4、put/Output.37Chapter 8:Operating System Support.43Chapter 9:Computer Arithmetic.48Chapter 10:Instruction Sets:Characteristics and Functions.61Chapter 11:Instruction Sets:Addressing Modes and Formats.72Chapter 12:Processor Structure and Function.77Chapter 13:Reduced Instruction Set Computers(RISCs).8

5、3Chapter 14:Instruction-Level Parallelism and Superscalar Processors.87Chapter 15:The IA-64 Architecture.93Chapter 16:Control Unit Operation.97Chapter 17:Microprogrammed Control.100Chapter 18:Parallel Processing.103Appendix A:Number Systems.112Appendix B:Digital Logic.113-5-CHAPTER 2COMPUTER EVOLUTI

6、ON ANDPERFORMANCE即 注 眶 四to umsmoNs2.1 In a stored program computer,programs are represented in a form suitable forstoring in memory alongside the data.The computer gets its instructions byreading them from memory,and a program can be set or altered by setting thevalues of a portion of memory.2.2 A m

7、ain memory,which stores both data and instructions:an arithmetic and logicunit(ALU)capable of operating on binary data;a control unit,which interprets theinstructions in memory and causes them to be executed;and input and output(VO)equipment operated by the control unit.2.3 Gates,memory cells,and in

8、terconnections among gates and memory cells.2.4 Moore observed that the number of transistors that could be put on a single chipwas doubling every year and correctly predicted that this pace would continue intothe near future.2.5 Similar or identical instruction set:In many cases,the same set of mac

9、hineinstructions is supported on all members of the family.Thus,a program thatexecutes on one machine will also execute on any other.Similar or identicaloperating system:The same basic operating system is available for all familymembers.Increasing speed:The rate of instruction execution increases in

10、 goingfrom lower to higher family members.Increasing Number of I/O ports:In goingfrom lower to higher family members.Increasing memory size:In going fromlower to higher family members.Increasing cost:In going from lower to higherfamily members.2.6 In a microprocessor,all of the components of the CPU

11、 are on a single chip.处BO近 史M T WRO目 上 运 M S2.1 This program is developed in HAYE98.The vectors A,B,and C are each stored in1,000 contiguous locations in memory,beginning at locations 1001,2001,and 3001,respectively.The program begins with the left half of location 3.A countingvariable N is set to 9

12、99 and decremented after each step until it reaches-1.Thus,the vectors are processed from high location to low location.-6-Location InstructionComments0999Constant(count N)11Constant21000Constant3LLOAD M(2000)Transfer A(I)to AC3RADD M(3000)Compute A(I)+B(I)4LSTOR M(4000)Transfer sum to C(I)4RLOAD M(

13、0)Load count N5LSUB M(l)Decrement N by 15RJUMP+M(6,20:39)Test N and branch to 6R if nonnegative6LJUMP M(6,0:19)Halt6RSTOR M(0)Update N7LADD M(l)Increment AC by 17RADD M(2)8LSTOR M(3,8:19)Modify address in 3L8RADD M(2)9LSTOR M(3,28:39)Modify address in 3R9RADD M(2)10LSTOR M(4,8:19)Modify address in 4

14、L10RJUMP M(3,0:19)Branch to 3L2.2 a.Opcode OperandI o o o o o o o i|000060000010 Ib.First,the CPU must make access memory to fetch the instruction.Theinstruction contains the address of the data we want to load.During the executephase accesses memory to load the data value located at that address fo

15、r a totalof two trips to memory.2.3 To read a value from memory,the CPU puts the address of the value it wants intothe MAR.The CPU then asserts the Read control line to memory and places theaddress on the address bus.Memory places the contents of the memory locationpassed on the data bus.This data i

16、s then transferred to the MBR.To write a value tomemory,the CPU puts the address of the value it wants to write into the MAR.TheCPU also places the data it wants to write into the MBR.The CPU then asserts theWrite control line to memory and places the address on the address bus and thedata on the da

17、ta bus.Memory transfers the data on the data bus into thecorresponding memory location.-8-2.4Address Contents08A LOAD M(OFA)STOR M(OFB)08B LOAD M(OFA)JUMP+M(08D)08C LOAD-M(OFA)STOR M(OFB)08DThis program will store the absolute value of content at memory location OF A intomemory location OFB.2.5 All

18、data paths to/from MBR are 40 bits.All data paths to/from MAR are 12 bits.Paths to/from AC are 40 bits.Paths to/from MQ are 40 bits.2.6 The purpose is to increase performance.When an address is presented to a memorymodule,there is some time delay before the read or write operation can beperformed.Wh

19、ile this is happening,an address can be presented to the othermodule.For a series of requests for successive words,the maximum rate is doubled.2.7 The discrepancy can be explained by noting that other system components aside from clockspeed make a big difference in overall system speed.In particular

20、,memory systems andadvances in I/O processing contribute to the performance ratio.A system is only as fast as itsslowest link.In recent years,the bottlenecks have been the performance of memorymodules and bus speed.2.8 As noted in the answer to Problem 2.7,even though the Intel machine may have afas

21、ter clock speed(2.4 GHz vs.1.2 GHz),that does not necessarily mean the systemwill perform faster.Different systems are not comparable on clock speed.Otherfactors such as the system components(memory,buses,architecture)and theinstruction sets must also be taken into account.A more accurate measure is

22、 to runboth systems on a benchmark.Benchmark programs exist for certain tasks,such asrunning office applications,performing floating point operations,graphicsoperations,and so on.The systems can be compared to each other on how longthey take to complete these tasks.According to Apple Computer,the G4

23、 iscomparable or better than a higher-clock speed Pentium on many benchmarks.2.9 This representation is wasteful because to represent a single decimal digit from 0through 9 we need to have ten tubes.If we could have an arbitrary number of thesetubes ON at the same time,then those same tubes could be

24、 treated as binary bits.With ten bits,we can represent 210 patterns,or 1024 patterns.For integers,thesepatterns could be used to represent the numbers from 0 through 1023.-9-2.10IcpmkrInstruction setarchitectureXXCompiler technologyXXXProcessorimplementationXXCache and memoryhierarchyXXSource:HWAN93

25、2.11 MIPS rate=/(CPI xlO6)2.12 a.We can express the MIPs rate as:(MIPS rate)/106=I J T.So that:Ic=T x(MIPS rate)/106.The ratio of the instruction count of the RS/6000 tothe VAX is x x 18/12x x 1=1.5.b.For the Vax,CPI=(5 MHz)/(l MIPS)=5.For the RS/6000,CPI=25/18=1.39.2.13 CPI=1.55;MIPS rate=25.8;Exec

26、ution time=3.87 ns.Source:HWAN932.14 a.Ultimately,the user is concerned with the execution time of a system,not itsexecution rate.If we take arithmetic mean of the MIPS rates of variousbenchmark programs,we get a result that is proportional to the sum of theinverses of execution times.But this is no

27、t inversely proportional to the sum ofexecution times.In other words,the arithmetic mean of the MIPS rate does notcleanly relate to execution time.On the other hand,the harmonic mean MIPSrate is the inverse of the average execution time.b.Arithmetic meanHarmonic MeanRankComputer A25.3 MIPS0.25 MIPS2

28、Computer B2.8 MIPS0.21 MIPS3Computer C3.25 MIPS2.1 MIPS1-10-HAPTER3COMPUTER FUNCTION ANDINTERCONNECTION处网播晚恒灵寻r QUESTIONS3.1 Processor-memory:Data may be transferred from processor to memory or frommemory to processor.Processor-yO:Data may be transferred to or from aperipheral device by transferring

29、 between the processor and an I/O module.Dataprocessing:The processor may perform some arithmetic or logic operation on data.Control:An instruction may specify that the sequence of execution be altered.3.2 Instruction address calculation(iac):Determine the address of the next instructionto be execut

30、ed.Instruction fetch(if):Read instruction from its memory locationinto the processor.Instruction operation decoding(iod):Analyze instruction todetermine type of operation to be performed and operand(s)to be used.Operandaddress calculation(oac):If the operation involves reference to an operand inmemo

31、ry or available via I/O,then determine the address of the operand.Operandfetch(of):Fetch the operand from memory or read it in from I/O.Data operation(do):Perform the operation indicated in the instruction.Operand store(os):Writethe result into memory or out to I/O.3.3(1)Disable all interrupts while

32、 an interrupt is being processed.(2)Define prioritiesfor interrupts and to allow an interrupt of higher priority to cause a lower-priorityinterrupt handler to be interrupted.3.4 Memory to processor:The processor reads an instruction or a unit of data frommemory.Processor to memory:The processor writ

33、es a unit of data to memory.I/Oto processor:The processor reads data from an I/O device via an I/O module.Processor to yO:The processor sends data to the I/O device.VO to or frommemory:For these two cases,an I/O module is allowed to exchange data directlywith memory,without going through the process

34、or,using direct memory access(DMA).3.5 With multiple buses,there are fewer devices per bus.This(1)reduces propagationdelay,because each bus can be shorter,and(2)reduces bottleneck effects.3.6 System pins:Include the clock and reset pins.Address and data pins:Include 32lines that are time multiplexed

35、 for addresses and data.Interface control pins:Control the timing of transactions and provide coordination among initiators andtargets.Arbitration pins:Unlike the other PCI signal lines,these are not sharedlines.Rather,each PCI master has its own pair of arbitration lines that connect it41-directly

36、to the PCI bus arbiter.Error Reporting pins:Used to report parity andother errors.Interrupt Pins:These are provided for PCI devices that must generaterequests for service.Cache support pins:These pins are needed to support amemory on PCI that can be cached in the processor or another device.64-bit B

37、usextension pins:Include 32 lines that are time multiplexed for addresses and dataand that are combined with the mandatory address/data lines to form a 64-bitaddress/data bus.JTAG/Boundary Scan Pins:These signal lines support testingprocedures defined in IEEE Standard 1149.1.公时加偃MS TO取足mb目MS3.1 Memo

38、ry(contents in hex):300:3005;301:5940;302:7006Step 1:3005 f IR;Step 2:3 f ACStep 3:5940 IR;Step 4:3+2=5 ACStep 5:7006 IR;Step 6:AC Device 63.2 1.a.The PC contains 300,the address of the first instruction.This value is loadedin to the MAR.b.The value in location 300(which is the instruction with the

39、value 1940 inhexadecimal)is loaded into the MBR,and the PC is incremented.These twosteps can be done in parallel.c.The value in the MBR is loaded into the IR.2.a.The address portion of the IR(940)is loaded into the MAR.b.The value in location 940 is loaded into the MBR.c.The value in the MBR is load

40、ed into the AC.3.a.The value in the PC(301)is loaded in to the MAR.b.The value in location 301(which is the instruction with the value 5941)isloaded into the MBR,and the PC is incremented.c.The value in the MBR is loaded into the IR.4.a.The address portion of the IR(941)is loaded into the MAR.b.The

41、value in location 941 is loaded into the MBR.c.The old value of the AC and the value of location MBR are added and theresult is stored in the AC.5.a.The value in the PC(302)is loaded in to the MAR.b.The value in location 302(which is the instruction with the value 2941)isloaded into the MBR,and the

42、PC is incremented.c.The value in the MBR is loaded into the IR.6.a.The address portion of the IR(941)is loaded into the MAR.b.The value in the AC is loaded into the MBR.c.The value in the MBR is stored in location 941.3.3 a.224=16 MBytesb.(1)If the local address bus is 32 bits,the whole address can

43、be transferred atonce and decoded in memory.However,because the data bus is only 16 bits,itwill require 2 cycles to fetch a 32-bit instruction or operand.-12-(2)The 16 bits of the address placed on the address bus cant access the wholememory.Thus a more complex memory interface control is needed to

44、latch thefirst part of the address and then the second part(because the microprocessorwill end in two steps).For a 32-bit address,one may assume the first half willdecode to access a row in memory,while the second half is sent later to accessa column in memory.In addition to the two-step address ope

45、ration,themicroprocessor will need 2 cycles to fetch the 32 bit instruction/operand.c.The program counter must be at least 24 bits.Typically,a 32-bit microprocessorwill have a 32-bit external address bus and a 32-bit program counter,unless on-chip segment registers are used that may work with a smal

46、ler program counter.If the instruction register is to contain the whole instruction,it will have to be32-bits long;if it will contain only the op code(called the op code register)thenit will have to be 8 bits long.3.4 In cases(a)and(b),the microprocessor will be able to access 216=64K bytes;theonly

47、difference is that with an 8-bit memory each access will transfer a byte,whilewith a 16-bit memory an access may transfer a byte or a 16-byte word.For case(c)zseparate input and output instructions are needed,whose execution will generateseparate I/O signals(different from the memory signals generat

48、ed with theexecution of memory-type instructions);at a minimum,one additional output pinwill be required to carry this new signal.For case(d),it can support 28=256 inputand 28=256 output byte ports and the same number of input and output 16-bitports;in either case,the distinction between an input an

49、d an output port is definedby the different signal that the executed input or output instruction generated.3.5 Clock cycle=-=125 ns)8 MHzBus cycle=4 x 125 ns=500 ns2 bytes transferred every 500 ns;thus transfer rate=4 MBytes/secDoubling the frequency may mean adopting a new chip manufacturing techno

50、logy(assuming each instructions will have the same number of clock cycles);doublingthe external data bus means wider(maybe newer)on-chip data bus drivers/latchesand modifications to the bus control logic.In the first case,the speed of the memorychips will also need to double(roughly)not to slow down