嵌入式处理器架构与程式设计课件.ppt
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1、嵌入式處理器架構與程式設計王建民中央研究院 資訊所2008年 7月ContentsnIntroductionnComputer ArchitecturenARM ArchitecturenDevelopment Tools:GNU Development ToolsnARM Instruction SetnARM Assembly LanguagenARM Assembly Programming:GNU ARM ToolChainnInterrupts and Monitor2Lecture 10Interrupts and MonitorOutlinenException Handling
2、 and Software InterruptsnELF:Executable and Linking FormatnARM Monitor and Program Loading4Normal Program Flow vs.ExceptionnNormally,programs execute sequentially(with a few branches to make life interesting)nNormally,programs execute in user mode nExceptions and interrupts break the sequential flow
3、 of a program,jumping to architecturallydefined memory locations nIn ARM,SoftWare Interrupt(SWI)is the“system call”exception5ARM ExceptionsnTypes of ARM exceptions lReset:when CPU reset pin is asserted lundefined instruction:when CPU tries to execute an undefined opcode lsoftware interrupt:when CPU
4、executes the SWI instruction lprefetch abort:when CPU tries to execute an instruction prefetched from an illegal addressldata abort:when data transfer instruction tries to read or write at an illegal address lIRQ:when CPUs external interrupt request pin is asserted lFIQ:when CPUs external fast inter
5、rupt request pin is asserted 6The Programmers ModelnProcessor Modes(of interest)lUser:the“normal”program execution mode.lIRQ:used for generalpurpose interrupt handling.lSupervisor:a protected mode for the operating system.nThe Register SetlRegisters R0R15+CPSRlR13:Stack Pointer(by convention)lR14:Li
6、nk Register(hardwired)lR15:Program Counter where bits 0:1 are ignored(hardwired)7TerminologynThe terms exception and interrupt are often confused nException usually refers to an internal CPU eventlfloating point overflow lMMU fault(e.g.,page fault)ltrap(SWI)nInterrupt usually refers to an external I
7、/O eventlI/O device request lreset nIn the ARM architecture manuals,the two terms are mixed together8What do SWIs do?nSWIs(often called software traps)allow a user program to“call”the OS that is,SWIs are how system calls are implemented.nWhen SWIs execute,the processor changes modes(from User to Sup
8、ervisor mode on the ARM)and disables interrupts.9SWI ExamplenTypes of SWIs in ARM Angel(axd or armsd)lSWI_WriteC(SWI 0)Write a byte to the debug channel lSWI_Write0(SWI 2)Write the nullterminated string to debug channel lSWI_ReadC(SWI 4)Read a byte from the debug channel lSWI_Exit(SWI 0 x11)Halt emu
9、lation this is how a program exits lSWI_EnterOS(SWI 0 x16)Put the processor in supervisor mode lSWI_Clock(SWI 0 x61)Return the number of centiseconds lSWI_Time(SWI 0 x63)Return the number of secs since Jan.1,197010What happens on an SWI?1nThe ARM architecture defines a Vector Table indexed by except
10、ion type nOne SWI,CPU does the following:PC 0 x08 nAlso,sets LR_svc,SPSR_svc,CPSR(supervisor mode,no IRQ)ADD r0,r0,r1 SWI 0 x10 SUB r2,r2,r0USER Programto R_Handlerto U_Handlerto S_Handlerto P_Handlerto D_Handler.to I_Handlerto F_HandlerVector Table(spring board)starting at 0 x00 in memory0 x000 x04
11、0 x080 x0c0 x100 x140 x180 x1c(Reset(Undef instr.)(SWI)(Prefetch abort)(Data abort)(Reserved)(IRQ)(FIQ)SWI Handler111What happens on an SWI?2nNot enough space in the table(only one instruction per entry)to hold all of the code for the SWI handler function nThis one instruction must transfer control
12、to appropriate SWI Handler nSeveral options are presented in the next slideADD r0,r0,r1 SWI 0 x10 SUB r2,r2,r0USER Programto R_Handlerto U_Handlerto S_Handlerto P_Handlerto D_Handler.to I_Handlerto F_HandlerVector Table(spring board)starting at 0 x00 in memory0 x000 x040 x080 x0c0 x100 x140 x180 x1c
13、(Reset(Undef instr.)(SWI)(Prefetch abort)(Data abort)(Reserved)(IRQ)(FIQ)SWI Handler212“Vectoring”Exceptions to HandlersnOption of choice:Load PC from jump table(shown below)nAnother option:Direct branch(limited range)ADD r0,r0,r1 SWI 0 x10 SUB r2,r2,r0USER ProgramLDR pc,pc,0 x100 LDR pc,pc,0 x100 L
14、DR pc,pc,0 x100 LDR pc,pc,0 x100LDR pc,pc,0 x100 LDR pc,pc,0 x100 LDR pc,pc,0 x100 LDR pc,pc,0 x100Vector Table(spring board)starting at 0 x00 in memory0 x000 x040 x080 x0c0 x100 x140 x180 x1cSWI Handler(S_Handler)2&A_Handler&U_Handler&S_Handler&P_Handler.“Jump”Table0 x1080 x10c0 x1100 x114.Why 0 x1
15、10?13What happens on SWI completion?nVectoring to the S_Handler starts executing the SWI handler nWhen the handler is done,it returns to the program at the instruction following the SWI nMOVS restores the original CPSR as well as changing pcADD r0,r0,r1 SWI 0 x10 SUB r2,r2,r0USER Programto R_Handler
16、to U_Handlerto S_Handlerto P_Handlerto D_Handler.to I_Handlerto F_HandlerVector Table(spring board)starting at 0 x00 in memory0 x000 x040 x080 x0c0 x100 x140 x180 x1c(Reset(Undef instr.)(SWI)(Prefetch abort)(Data abort)(Reserved)(IRQ)(FIQ)3MOVS pc,lrSWI Handler(S_Handler)14How to determine the SWI n
17、umber?nAll SWIs go to 0 x08ADD r0,r0,r1 SWI 0 x10 SUB r2,r2,r0USER Programto R_Handlerto U_Handlerto S_Handlerto P_Handlerto D_Handler.to I_Handlerto F_HandlerVector Table(spring board)starting at 0 x00 in memory0 x000 x040 x080 x0c0 x100 x140 x180 x1c(Reset(Undef instr.)(SWI)(Prefetch abort)(Data a
18、bort)(Reserved)(IRQ)(FIQ)SWI Handler must serve as clearinghouse for differentSWIsMOVS pc,lrSWI Handler(S_Handler)15SWI Instruction FormatnExample:SWI 0 x1824bit“comment”field(ignored by processor)1 1 1 1cond02324273128SWI number16Executing SWI InstructionOn SWI,the processor(1)copies CPSR to SPSR_S
19、VC(2)set the CPSR mode bits to supervisor mode(3)sets the CPSR IRQ to disable(4)stores the value(PC+4)into LR_SVC(5)forces PC to 0 x08 ADD r0,r0,r1 SWI 0 x10 SUB r2,r2,r0USER Programto R_Handlerto U_Handlerto S_Handlerto P_Handlerto D_Handler.to I_Handlerto F_HandlerVector Table(spring board)startin
20、g at 0 x00 in memory0 x000 x040 x080 x0c0 x100 x140 x180 x1c(Reset(Undef instr.)(SWI)(Prefetch abort)(Data abort)(Reserved)(IRQ)(FIQ)LDR r0,lr,#4BIC r0,r0,#0 xff000000R0 holds SWI numberMOVS pc,lrSWI Handler(S_Handler)24bit“comment”field(ignored by processor)1 1 1 1cond17Jump to“Service Routine”ADD
21、r0,r0,r1 SWI 0 x10 SUB r2,r2,r0USER Programto R_Handlerto U_Handlerto S_Handlerto P_Handlerto D_Handler.to I_Handlerto F_HandlerVector Table(spring board)starting at 0 x00 in memory0 x000 x040 x080 x0c0 x100 x140 x180 x1c(Reset(Undef instr.)(SWI)(Prefetch abort)(Data abort)(Reserved)(IRQ)(FIQ)LDR r0
22、,lr,#4BIC r0,r0,#0 xff000000switch(r0)case 0 x00:service_SWI1();case 0 x01:service_SWI2();case 0 x02:service_SWI3();MOVS pc,lrSWI Handler(S_Handler)24bit“comment”field(ignored by processor)1 1 1 1condOn SWI,the processor(1)copies CPSR to SPSR_SVC(2)set the CPSR mode bits to supervisor mode(3)sets th
23、e CPSR IRQ to disable(4)stores the value(PC+4)into LR_SVC(5)forces PC to 0 x08 18Problem with The Current HandlerOn SWI,the processor(1)copies CPSR to SPSR_SVC(2)set the CPSR mode bits to supervisor mode(3)sets the CPSR IRQ to disable(4)stores the value(PC+4)into LR_SVC(5)forces PC to 0 x08 ADD r0,r
24、0,r1 SWI 0 x10 SUB r2,r2,r0USER Programto R_Handlerto U_Handlerto S_Handlerto P_Handlerto D_Handler.to I_Handlerto F_HandlerVector Table(spring board)starting at 0 x00 in memory0 x000 x040 x080 x0c0 x100 x140 x180 x1c(Reset(Undef instr.)(SWI)(Prefetch abort)(Data abort)(Reserved)(IRQ)(FIQ)LDR r0,lr,
25、#4BIC r0,r0,#0 xff000000switch(r0)case 0 x00:service_SWI1();case 0 x01:service_SWI2();case 0 x02:service_SWI3();MOVS pc,lrSWI Handler(S_Handler)What was in R0?User program may have been using this register.Therefore,cannot just use it must first save it 19Full SWI HandlerS_Handler:SUB sp,sp,#4 leave
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