双语(第10章)--10.-Behavioral-and-Structural-Descriptio.ppt

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1、1 10.Behavioral and Structural Descriptions 10.1 An example 10.2 The dataflow description10.3 Structural VHDL10.4 Processes10.5 Sequential and concurrent VHDL2 10.1 An example Example:a Four-bit adder sum=x+y;Describe a 4-bit adder in VHDL 1111110011101010100110110010100110000000Carry outSumCarry in

2、yx3 10.1 An example Circuit diagram 4 10.2 The dataflow description1.Local signals Full adder circuit with the internal nodes n1,n2,n3,n4 are the internal nodes of the circuit 6 10.2 The dataflow descriptionARCHITECTURE number3 OF fulladd IS SIGNAL n1,n2,n3,n4:STD_LOGIC;BEGIN n1=x XOR y;sum=cin XOR

3、n1;n2=x AND y;n3=cin AND x;n4=y AND cin;cout=n2 OR n3 OR n4;END ARCHITECTURE number3;the VHDL description is changed toLocal signals n1,n2,n3 and n4 as part of the description 7 10.2 The dataflow description2.Concurrent processing ARCHITECTURE number3 OF fulladd IS SIGNAL n1,n2,n3,n4:STD_LOGIC;BEGIN

4、 n1=x XOR y;sum=cin XOR n1;n2=x AND y;n3=cin AND x;n4=y AND cin;cout x(0),y=y(0),cin=cin,sum=sum(0),cout=carry(1);This is called named association.With named association,the order doesnt matter.19 10.4 Processes 1.Sensitivity listsARCHITECTURE simple OF fulladd IS -1BEGIN -2 cout=(x AND y)OR(cin AND

5、 x)OR(y AND cin);-3 sum=cin XOR x XOR y;-4END ARCHITECTURE simple;-5Statement 3 will run whenever a right hand side value changes.So it runs when x,y or cin changes.In the jargon of VHDL,statement 3 is sensitive to signals x,y,cin.Its sensitivity list is x,y,cin.A change in a signal is called an eve

6、nt on that signal.So statement 3 runs whenever there is an event on a signal on its sensitivity list.20 10.4 Processes Statements 3 and 4 are concurrent,i.e.they are both active at the same time,and are triggered by an event on a signal on their sensitivity lists.2.The structure of a process PROCESS

7、(sensitivity list)BEGIN Statement 1;Statement 2;Statement 3;END PROCESS;21 10.4 Processes(1)The process waits until it is triggered by an event on one of the signals in its sensitivity list.(2)When it is triggered it executes each of the statements in its body sequentially.(3)During execution of the

8、 process,all signal values are frozen and are not updated or changed in any way during the execution of the process(4)The LHS signals all receive their new value after the process has suspended its execution.22 10.4 Processes 3.The WAIT statement Instead of using a sensitivity list,we can the timing

9、 of execution of a process by using a WAIT statement.ARCHITECTURE using_wait OF fulladd IS BEGIN PROCESS BEGIN WAIT ON x,y,cin;cout=(x AND y)OR(cin AND x)OR(y AND cin);sum=cin XOR x XOR y;END PROCESS;END ARCHITECTURE using_wait;24 10.5 Sequential and concurrent VHDL1.Sequential and concurrent condit

10、ionals（1）Sequential IF blockIF condition_1 THEN sequence of statements;ELSIF condition_2 THEN sequence of statements;ELSE sequence of statements;END IF;25 10.5 Sequential and concurrent VHDL（2）Concurrent WHEN statement a=value1 WHEN condition1 ELSE value2 WHEN conditon2 ELSE value3;26 10.5 Sequentia

11、l and concurrent VHDLThe operation of selecting one of the data lines to the output y depending on the value of address is accomplished in concurrent VHDL using a SELECT statement:ARCHITECTURE concurrent OF mux4to1 ISBEGINWITH address SELECT y y y y y=data(1);END CASE;END PROCESS;END ARCHITECTURE sequential;29