单片机【经典外文翻译】-max-ii-cpld系列概述及应用(英文+译文)毕业论文.doc





《单片机【经典外文翻译】-max-ii-cpld系列概述及应用(英文+译文)毕业论文.doc》由会员分享,可在线阅读,更多相关《单片机【经典外文翻译】-max-ii-cpld系列概述及应用(英文+译文)毕业论文.doc(6页珍藏版)》请在淘文阁 - 分享文档赚钱的网站上搜索。
1、MAX II CPLD: Lowest Power, Lowest Cost CPLD Family Ever Alteras MAX II family of CPLD family are the lowest power, lowest cost CPLDs ever. MAX II CPLD family is based on a groundbreaking architecture that delivers the lowest power and the lowest cost per I/O pin of any CPLD family. With the introduc
2、tion of the MAX IIZ CPLD, there are now three variants that all use the same innovative CPLD architecture: MAX II CPLD MAX IIG CPLD MAX IIZ CPLD This instant-on, non-volatile CPLD family targets general-purpose, low-density logic andportable applications, such as cellular handset design. In addition
3、 to delivering the lowest cost for traditional CPLD designs, the MAX II CPLD drives power and cost improvements to higher densities, enabling you to use a MAX II CPLD in place of a higher power or higher cost ASSP or and standard-logic CPLD. Advanced CPLD features The MAX II CPLD enables a high leve
4、l of functional integration to reduce system design costs. This section describes the advanced features found in every MAX II CPLD. Low power CPLD One-tenth the power consumption (compared toa previous-generation 3.3-VMAX CPLD) 1.8-V core voltage for reduced power consumption and increased reliabili
5、ty CPLD industrys lowest standby specification, allowing longer usein battery powered applications Auto start/stop capability for turning off the CPLD when not in use Cost-optimized architecture Four times the density at half the price (compared to previous MAXCPLD generations) Designedfor minimum d
6、ie size, giving the lowest cost per I/O pin in the industry High performance Support for internal clock frequency rates of up to 300 MHz Twicethe performance (compared to a 3.3-V MAX CPLD) Unique features On-board oscillatorand userflashmemory Reduces chip count by eliminating discrete oscillators o
- 配套讲稿:
如PPT文件的首页显示word图标,表示该PPT已包含配套word讲稿。双击word图标可打开word文档。
- 特殊限制:
部分文档作品中含有的国旗、国徽等图片,仅作为作品整体效果示例展示,禁止商用。设计者仅对作品中独创性部分享有著作权。
- 关 键 词:
- 经典外文翻译 单片机 经典 外文 翻译 max ii cpld 系列 概述 应用 英文 译文 毕业论文

限制150内