计算机系统组成与体系结构答案.pdf

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1、SOLUTIONS MANUALComputer Systems Organizationand ArchitectureJohn D.CarpinelliCopyright 2001,Addison Wesley Longman-All Rights ReservedTable of ContentsChapter 1 1Chapter 2 8Chapter 3 18Chapter 4 21Chapter 5 33Chapter 6 45Chapter 7 59Chapter 8 80Chapter 9 92Chapter 10 100Chapter 11 106Chapter 12.116

2、Computer Systems Organization and Architecture-Solutions ManualChapter 12.a)w Xyz wx xz Vwx+xz+yb)w Xyz w+x+y+z0 0 0 0 0 0 1 1 0 0 0 0 00 0 0 1 0 0 1 1 0 0 0 1 10 0 1 0 0 0 0 0 0 0 1 0 10 0 1 1 0 0 0 0 0 0 1 1 10 1 0 0 0 0 1 1 0 1 0 0 10 1 0 1 0 1 1 1 0 1 0 1 10 1 1 0 0 0 0 0 0 1 1 0 10 1 1 1 0 1 0

3、1 0 1 1 1 11 0 0 0 0 0 1 1 1 0 0 0 11 0 0 1 0 0 1 1 1 0 0 1 11 0 1 0 0 0 0 0 1 0 1 0 11 0 1 1 0 0 0 0 1 0 1 1 11 1 0 0 1 0 1 1 1 1 0 0 11 1 0 1 1 1 1 1 1 1 0 1 11 1 1 0 1 0 0 1 1 1 1 0 11 1 1 1 1 1 0 1 1 1 1 1 1c)wX y z w x y z wxyz w y y z w 3 3z+w xyz+卬*$z+w y y z0 0 0 0 0 0 0 0 00 0 0 1 0 0 0 0 0

4、0 0 1 0 0 0 1 0 10 0 1 1 1 0 0 0 10 1 0 0 0 0 0 0 00 1 0 1 0 0 0 0 00 1 1 0 0 0 0 1 10 1 1 1 0 1 0 0 11 0 0 0 0 0 0 0 01 0 0 1 0 0 0 0 01 0 1 0 0 0 0 0 01 0 1 1 0 0 0 0 01 1 0 0 0 0 0 0 01 1 0 1 0 0 0 0 01 1 1 0 0 0 0 0 01 1 1 1 0 0 0 0 0Copyright 2001 Addison Wesley-All Rights Reserved Page 1Comput

5、er Systems Organization and Architecture-Solutions Manual工 a b ab(aby a b a+6.0 0 0 1 1 1 10 1 0 1 1 0 11 0 0 1 0 1 11 1 1 0 0 0 0a b a+b(a+a b ab0 0 0 1 1 1 10 1 1 0 1 0 01 0 1 0 0 1 01 1 1 0 0 0 0a)b)c)4wxyz 00 01 1 1 1000 1|001 01 1161V lJ.00 0o o)000C t,D 0 001 0 k.i)011 0 0J1 R10m0a)5卬 二 夕+卬+wx

6、y+wx 2 or卬 夕 2+xyz+wyz，V+w 旷+xz+xyorx 2+w 旷+xz+y26.a)v v zz+xywxyz 00 01 11 10()0 0 0 n011 JX 1,i11 0,1 X010 0 X X 0b)wxyz 00 01 1 1 1000显 1 iX)01 0 X X 01 1 0 0 X 010修 X XX17.a)w xyW 00 01-0 011 100111100 0 00 1n 0(L u 7 1)0 0 0 0wx+xz+w y z y z+孙，+wzwxyz,00 0100011 11011 100 1 0 11 0 1 00 1 0 11 0

7、 1 0Already tninitnal8.9.wx+xyCopyright 2001 Addison Wesley-All Rights Reserved Page 2Computer Systems Organization and Architecture-Solutions Manual10.a)11.Change the AND gates to NAND gates.The rest of the circuit is unchanged.12.Remove the tri-state buffers and do one of the following:a)Change ea

8、ch 2-input AND gate to a 3-input AND gate.Each gates1 inputs should be its two originalinputs and E,orb)Have each AND gates output serve as an input to another 2-input AND gate,one gate fbr each originalAND gate.The second input to the new 2-input AND gates is E.13.14.Copyright 2001 Addison Wesley-A

9、ll Rights Reserved Page 3Computer Systems Organization and Architecture-Solutions Manual15.Set up Karnaugh maps for each output,then develop minimal logic expressions and design the appropriatelogic circuits.(XY)=XiYIl+XoY/Yo1 X/X。(X=Y)=Xj XoYiYo+X,XoYirY0+XIXO,YIYo 1+X/XohYo=(X,力)。%)(XY)=X/tYl+XJ,X

10、o，Y o+Xo，Y/Yo16.。3=X2Y2+(X2 Y2)(XIYI+(X/YiXXoYo+(X。%)C。)C4=X3Y3+(X.,Y3)(X2Y2+(X 2 Y2)(XlYl+(Xi YXoYo+(X。%)Q)17.Copyright 2001 Addison Wesley-All Rights ReservedPage 4Computer Systems Organization and Architecture-Solutions Manual18d=X2X0+XX+X/X。+X2X1X0X3X2NX0 00 01 11 10c o Q|0H O10UT 10()1000 x0f=X

11、3+X2Xo，+X2Xi+XllXo,e=X2Xl,+X0X3XX,X0 00 01 11 1000 0 I 0 I 0|Uo i-6 6 6 o-“X X X 国 io|o I o I x|C=X2%X。，X3X K,X 00 01 11 10f=XlX0+X3fX2X0+X2fXICopyright 2001 Addison Wesley-All Rights Reserved Page 5Computer Systems Organization and Architecture-Solutions Manual20.The four inputs can be in one of 24

12、(=4!)possible orders.Since each sorter has two possible states(MAX=X MIN=X,or MAX=Y MIN=X),sorters can have up to T states.Four sorters can have only 24=16states,not enough to sort all 24 possible input orders.Five sorters have 25=32 states,which could besufficient.(This argument establishes a lower

13、 bound;it does not guarantee the existence of a 5-sorternetwork that can sort four inputs.Since the sorting network of Figure 1.24(b)matches this bound,it is aminimal network.)21.a)22.A flip-flop is clocked if the increment signal and clock are asserted,and all flip-flops to its right are 1.23.Each

14、clock is driven by Q of the flip-flop to its right instead of Q.The clock of the rightmost flip-flop isunchanged.All other signals are unchanged.XzXX/X。00 01 11 10Copyright 2001 Addison Wesley-All Rights Reserved Page 6Computer Systems Organization and Architecture-Solutions ManualCopyright 2001 Add

15、ison Wesley-All Rights Reserved Page 7Computer Systems Organization and Architecture-Solutions ManualChapter 22.Present State SgKTTTR Next Stateuu _UTT2TT2T3g2TuoTV五 yTggigKTU 1 1 u3.Add the following states to the state table.Since all additions are self-loops,it is not necessary to changethe state

16、 diagram.Present State ch IoNext State R G AS NOCAR0 0 1s NOCAR1 0 0S NOCAR0 1 0SNOCAR1 0 0s NOCAR0 1 1sNOCAR1 0 0SPMD 1 0 1S P.M D0 1 0S PA I I 1 1 0SPAII,0 1 0SPA ID1 1 1SPA ID0 1 0s CHEAT0 0 1s CH EAT1 0 1S CHEAT0 1 0S CH EAT1 0 1S CHEAT0 1 1S CH EAT1 0 1Copyright 2001 Addison Wesley-All Rights R

17、eserved Page 8Computer Systems Organization and Architecture-Solutions ManualCopyright 2001 Addison Wesley-All Rights Reserved Page 9Computer Systems Organization and Architecture-Solutions Manual5.6.Address Data(Mealy)Data(Moore)0000 0000 00000001 0010 00100010 0100 01000011 0110 01100100 1000 1000

18、0101 1010 10100110 1101 11000111 1110 11101000 0000 00001001 0010 00101010 0100 01001011 0110 01101100 1000 10011101 1010 10111110 1101 1100n i l 1110 11107.Present State I Next State M00 0 00 000 1 01 001 0 00 001 1 10 010 0 1 1 010 1 10 01 1 0 00 11 1 1 01 1N=P/Pol+P F。NO=P/PO7+P F O T+P R JM=P RC

19、opyright 2001 Addison Wesley-All Rights Reserved Page 10Computer Systems Organization and Architecture-Solutions Manual8.9.Address Data(Mealy)Data(Moore)000 000 000001 010 010010 000 000Oil 100 100100 111 110101 100 100110 000 001111 010 Oil10.State value assignments(P3 P.S()=0000 S5=0001 S/o=0010 S

20、 1 5=0011 S 2 0=010025=0101 S30=00 SPAID=0 SN0CAR=1000 SCHEAT=1001M=c，M=P/Chlo+尸 3(匕+尸/)C/o+P/(P2+PFo)C“Io+P2CII,IO,N尸 P3P2+匕+Po)ChIo+匕(尸 2+P/K W+PNPiP。+P/PJ+P2PlPo)CIl,Io+P.PoChIoN=PAP2+匕+P Q C。+PNPo+P2Pi)CIlI0,+P式 Po+P2PDCW0+P3 尸。C/4/+P3Poe+2 3(尸 2+匕+尸 0)。R=SPAIDG=SPAID4=S cH E A T1 1.State value

21、assignments(Pj-Po)：S()=0000 S5=0001 Sl0=0010=0011 520=010025=0101 S30=0110 SPAID=0111 SNOCAR=1000 SCHEAT=1001N3=CM=P H+P/(P2+尸 3(尸 2+P/P o)C/0+P2Ch，Io,N】=P3P2+匕+P0)ChI0+PNP2+尸+PAP1P0+PFo+P2PiPo)CIl,Io+PiPoChVN0=匕(P 2+匕+PQCWo+PNPo+P2PI)C1II(),+尸 3 W+P2PI)CII 7。+尸 3尸。0+P3Poe+尸 3(尸 2+匕+尸。)。R=GG=P3P2+PC

22、hlo+P；P2Poeh+P；P2PA h+Io)+P3T2PF0CA=匕(尸 2+匕+尸。)仁 Copyright 2001 Addison Wesley-All Rights Reserved Page 1 1Computer Systems Organization and Architecture-Solutions Manual12.Address DataOOOOXXX 1001101 1001101 1001101 1001101 0000100 0001100 0010100 01011000001XXX 1001101 1001101 1001101 1001101 0001

23、100 0010100 0011100 01101000010XXX 1001101 1001101 1001101 1001101 0010100 0011100 0100100 01110100011XXX 1001101 1001101 1001101 1001101 0011100 0100100 0101100 01110100100XXX 1001101 1001101 1001101 1001101 0100100 0101100 0110100 01110100101XXX 1001101 1001101 1001101 1001101 0101100 011010001110

24、1001110100110XXX 1001101 1001101 1001101 1001101 01101000111010011101001110100111XXX 1000100 1000100 1000100 1000100 0111010 0111010 0111010 01110101000XXX 1000100 1000100 100010()1000100 0000100 000()10()0000100 00001 001001XXX 1001101 1001101 1001101 1001101 000010()000010()0000100 00001 001010XXX

25、 1000100 1000100 1000100 1000100 1000100 1000100 1000100 100010010HXXX 1000100 1000100 1000100 1000100 1000100 1000100 100010()1000100u o o x x x 1000100 1000100 1000100 1000100 1000100 1000100 1000100 10001001101XXX 1000100 1000100 1000100 1000100 1000100 1000100 1000100 10001001110XXX 1000100 1000

26、100 1000100 1000100 1000100 1000100 1000100 10001001111XXX 1000100 1000100 1000100 1000100 1000100 1000100 1000100 1000100N2=P2Po，+P2U,+PlPoUN1=PIPO，+PI U,+P2,P1,POUNo=PoU+PoUC=P2,PI,POV,+P2PI,POUv2=P2P1P0U+尸 2匕 了。+P zP fP MVy=PPiPoU+PzHPo+PzPjPoU%=(尸 2+P M oU+(P2+Pj)PoU15.All possible next state va

27、lues are already used.Copyright 2001 Addison Wesley-All Rights Reserved Page 12Computer Systems Organization and Architecture-Solutions Manual16.State value assignments(P3-Po)：So=0000 55=0001 5川=0010 5/5=0011$20=0100S 2 5=0101$30=0110 SpiD=0111 SOCAR=1000 SCHEAT=1001 54=1010ion sc=iioo sD=noi sE=mo

28、sF=m iAdd to state diagram:Add to state table:Present State Ch IoNext State R G A1010 X X X 1000 0 0 01011 X X X 1000 0 0 01100 X X X 1000 0 0 01101 X X X 1000 0 0 01110 X X X 1000 0 0 01111 X X X 1000 0 0 0N3=C,P3(P2+PI)M=P H+匕(尸 2+匕)C/J+PAP2+匕 Po)C/o+P2Ch，IoNi=P/(P2+P/+Po)CIlIo+尸 3(P2+P j)W+PPiPo+

29、P】Po+P2PjPo)CI“o+PiPoChIo1No=PNP?+匕+W h l o+P3P0+P 2P oeW+P3 W+P2PDCW0+P；PoCh7o，+P3Poe+尸 3(尸 2+匕+尸。)。R=SPAIDG=S p A IDA=S C H E A T17.N3=P2P/P0U+尸 3(尸 2,+P/+Po+N2=P3P2(Po+/2匕+PfPFoUN=P/(尸 2+尸/)+PzP/PoU+PjUN O=(P3+P2)PIV+P3P2U+P0U1C=P2Pl,Pof匕=尸 3尸/尸。+尸 3尸 2尸 0匕=-3 巧 尸。+尸 2尸/尸。V0=P3lP2rP0+P2PP0 P3PlfP

30、0Copyright 2001 Addison Wesley-All Rights Reserved Page 13Computer Systems Organization and Architecture-Solutions Manual18.raCopyright 2001 Addison Wesley-All Rights Reserved Page 14Computer Systems Organization and Architecture-Solutions Manual20.States are of the form ABCYZ,where ABC=0 if a playe

31、r may signal,or 1 if the player may not signal.YZrepresents the player answering the question(01=player 1,10=player 2,11=player 3,00=no player).Although not shown in the diagram,there is an arc from every state back to state 00000 with condition R.Address DataXXXXX XXIX 00000 00000000 ooox 00000 000

32、00000()1 ox 00001 00000000 100X 00010 00000000 110X 00011 00000001 x x o o 00001 10000001 XX01 10000 10000010 x x o o 00010 01000010 XX01 01000 01000011 x x o o 00011 00100011 XX01 00100 00100100 ooox 00100 00000100 010X 00101 00000100 100X 00110 00000100 110X 00100 00000101 x x o o 00101 10000101 X

33、X01 10100 100Address Data00110 x x o o 0011001000110XX01 0110001001000 x o o x 01000 00001000 010X 01001 00001000 110X 01011 00001001 x x o o()1001 10001001 XX01 11000 10001011 x x o o 01011 00101011 XX01 01100 00101100 ooox()1100 00()01100 010X 01101 00001100 1X0X 01100 00001101 x x o o 01101 10001

34、101 XX01 11100 10010000 o x o x 10000 00010000 100X 10010 00010000 110X 10011 000Address Data10010 x x o o 1001001010010 XX01 11000 01010011 x x o o 10011 00110011 XX01 10100 00110100 o x o x 10100 00010100 100X 10110 00010100 110X 10100 00010110 x x o o 1011001010110XX01 1110001011000 o x o x 11000

35、 00011000 100X 11000 00011000 110X 11011 00011011 x x o o 11011 00111011 XX01 11100 00111100 x x o x 11100 000AH others()000()000Copyright 2001 Addison Wesley-All Rights Reserved Page 15Computer Systems Organization and Architecture-Solutions Manual21.States are of the form ABCYZ,where ABC=0 if a pl

36、ayer may signal,or 1 if the player may not signal.YZrepresents the player answering the question(01=player 1,10=player 2,11=player 3,00=no player).Although not shown in the diagram,there is an arc from every state back to state 00000 with condition R.Address Data Address DataXXXXX XXIX 00000 000 001

37、10 xxoo 0011001000000 ooox 00000 000 00110XX01 01100 00000000 01 ox 00001 100 0100()xoox 01000 00000000 100X 00010 010 01000 010X 01001 10000000 110X 00011 001 01000 110X 01011 00100001 xxoo 00001 100 01001 xxoo 01001 10000001 XX01 10000 000 01001 XX01 11000 00000010 xxoo 00010 010 01011 xxoo 01011

38、00100010 XX01 01000 000 01011 XX01 01100 00000011 xxoo 00011 001 01100 ooox 01100 00000011 XX01 00100 000 01100 010X 01101 1000010()ooox 00100 000()1100 1X0X 01100 00000100 010X 00101 100 01101 xxoo 01101 10000100 100X 00110010 01101 XX01 11100 00000100 110X 00100 00()10000 oxox 10000 00000101 xxoo

39、00101 100 10000 100X 1001001000101 XX01 10100 000 10000 110X 10011 001Address Data10010 xxoo 10010 01010010 XX01 11000 00010011 xxoo 10011 00110011 XX01 10100 00010100 oxox 10100 00010100 100X 1011001010100 110X 10100 00010110 xxoo 1011001010110XX01 11100 00011000 oxox 11000 00011000 100X 11000 0001

40、1000 110X 11011 001n o n xxoo 11011 001n o n x x o i 11100 00011100 x x o x 11100 000All others 00000 000Copyright 2001 Addison Wesley-All Rights Reserved Page 16Computer Systems Organization and Architecture-Solutions Manual22.23.24.25.Po：PoXY should be P()X TB:Po should be P。26.CLR:Counter input D

41、():A:OXK should be XYOXY should be O XY1 should be 027.Address Correct Data0011 011100100 010H1011 00111Copyright 2001 Addison Wesley-All Rights Reserved Page 17Computer Systems Organization and Architecture-Solutions ManualChapter 31.a)Data movement b)Data operation C)Program control d)Data operati

42、on e)Data operation2.a)Data operation b)Program control C)Data movement d)Data movement e)Data operation3.a)Direct b)Implied c)Implicit4.a)Implicit b)Direct c)Implicit5.a)Implicit b)Direct C)Implicit6.a)Register Direct b)Immediate C)Implicit d)Immediate e)Direct7.a)Implicit b)Direct C)Indirect d)Reg

43、ister Indirect e)Register Direct8.a)Register Direct b)Register Indirect C)Implicit d)Implicit e)ImmediateMULADDPOPX9.a)AC=1 1 b)AC=12 c)AC=10 d)AC=11 e)AC=10 f)A C=33 g)AC=4110.a)AC=11 b)AC=12 C)AC=30 d)AC=31 e)AC=10 f)AC=23 g)4C=3111.a)AC=Il b)A C=12 C)AC=20 d)A C=2 e)AC=10 f)AC=43 g)AC=2112.a)MULX

44、,B,C b)MOV X,B C)LOADB d)PUSH AADD X,X,A MUL X,C MULC PUSHBADD X,X,D ADD X,A ADDA PUSH CADD X,D ADDDSTORE XMULPUSH DADDADDPOPX13.a)MUL TAB b)MOV T,A c)LOAD A d)PUSH AMUL T,T,C MUL T,B MULB PUSHBADD X,E,F MUL T,C MULC MULMUL X,X,D MOV X,E STORET PUSHCADD X,X,T ADD X,F LOADE MULMUL X,D ADDF PUSHDADD X

45、,T MULTDADDTSTORE XPUSHEPUSHFADDCopyright 2001 Addison Wesley-All Rights Reserved Page 18Computer Systems Organization and Architecture-Solutions ManualPOPX14.a)MUL X,B,CSUB X,A,Xb)MOV T,BMUL T,CC)LOADBMULCd)PUSH APUSH BMUL T,E,F MOV X,A STORET PUSHCADD T,T,D SUB X,T LOAD A MULMUL X,X,T MOV T,E SUBT

46、 SUBMUL T,F STORE X PUSH DADD T,D LOADE PUSHEMUL X,T MULF PUSHFADDD MULMULX ADDSTORE X MUL15.Processor Time per instruction#Instructions Total time0 35 ns 4 140 ns1 50 ns 3 150 ns2 70 ns 2 140 ns3 100 ns 1 100 ns fastest16.Processor Time per instruction#Instructions Total time0 35 ns 8 280 ns1 50 ns

47、 5 250 ns fastest2 70 ns 4 280 ns3 100 ns 3 300 ns17.Processor Time per instruction#Instructions Total time0 35 ns 12 420 ns 4 fastest1 50 ns 9 450 ns2 70 ns 7 490 ns3 100 ns 5 500 ns18.Processor Time per instruction#Instructions Total time0 35 ns 12 420 ns-fastest1 50 ns 1 1 550 ns2 70 ns 8 560 ns3

48、 100 ns 5 500 ns19.LDA C lUOiH“LDAC 1UU6HMVAC ADDLDAC 1002H MVACADD LDAC 1007HMVAC ADDLDAC 1003H MVACADD LDAC 1008HMVAC ADDLDAC 1004H MVACADD LDAC 1009HMVAC ADDLDAC 1005H MVACADD LDAC 100AHMVAC ADD1STAC 1000HCopyright 2001 Addison Wesley-All Rights Reserved Page 19Computer Systems Organization and A

49、rchitecture-Solutions Manual20.LXI H,1001HLoop:MVI B,0AHXRA AADDMINXHDCRBJNZ LoopSTA 1000H21.Loop:CLACINACSTAC FAINACSTAC FBSTAC CountSTAC FNMVACLDACSUBJMPZ DoneLDAC FAMVACLDAC FBADDSTAC FALDAC CountINACSTAC CountMVACLDACnSUBJMPZ Done A1FA=1FB=2Count=2FN=2Ifn=2 then doneFA=FA+FBCount=Count+1If Count

50、=n thendone,result in FA LDAC kBMVACLDAC FAADDSTAC FBLDAC CountINACSTAC CountMVACLDACnSUBJMPZ DoneBJUMP LoopDoneA:LDAC FASTAC FNJUMP DoneDoneB:LDAC FBSTAC FNDone.FB=FB+FACount=Count+1If Count=n thendone,result in FBNot done,loop backFN=FAFN=FB22.Loop:Done.LDA MOV D,AMVI B MVI A,2MOV C,ADCRDDCRDJZ Do