(8.4.3)--Ch_03-System Buses计算机组成原理.ppt

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1、 计算机组成原理 -双语教学课件双语教学课件William Stallings Computer Organization and Architecture6th EditionChapter 3System Buses3.1 computer component Program ConceptHardwired systems are inflexibleProgrammed manually by setting switches and plugging&unplugging cables General purpose hardware can do different tasks,g

2、iven correct control signals(go to)Instead of re-wiring,supply a new set of control signalsWhat is a program?A sequence of stepsFor each step,an arithmetic or logical operation is doneFor each operation,a different set of control signals is needed一系列的步骤一系列的步骤每一步，完成一个算术或逻辑操作每一步，完成一个算术或逻辑操作每一次操作，需要一组不

3、同的控制信号每一次操作，需要一组不同的控制信号Function of Control UnitFor each operation a unique code is providede.g.ADD,MOVEA hardware segment accepts the code and issues the control signalsWe have a computer!要为每一个操作提供一个唯一的编码要为每一个操作提供一个唯一的编码(相互区别相互区别)硬件部分接受该编码并发布控制信号硬件部分接受该编码并发布控制信号ComponentsThe Control Unit and the Ari

4、thmetic and Logic Unit constitute the Central Processing UnitData and instructions need to get into the system and results outInput/outputTemporary storage of code and results is neededMain memory控制器和运算器构成控制器和运算器构成CPU系统要输入数据和指令，输出结果系统要输入数据和指令，输出结果需要暂时存储需要暂时存储(数据的和指令的数据的和指令的)编码和结果编码和结果Computer Compon

5、ents:Top Level ViewStructure of components(charter 2 page 19)Memory structure:Memory contains of N storage locations,called word,of M digits(bits).Both data and instructions are stored there.Data(numbers)are represented in binary form.Instructions also are binary code form.Each storage location has

6、a serial number to sign its position,the serial number calls address,from 0 to N-1.Memory structureAn instruction wordAn data wordAddressfrom o to N-1I/O structureIn an abstracted and simplified view,I/O is similar to memory.Some words of storage CPU structureSome registers:Memory buffer register(MB

7、R):contains a word to be stored into memory,or a word just received from memory.Memory Address Register(MAR):specifies the address in memory of read/write a word(data or instruction).Instruction buffer Register(IBR):holds temporarily an instruction code just fetched from memory CPU structureInstruct

8、ion Register(IR):contains opcode of Instruction to be decoded.Program counter(PC):contains the address of the next instruction in memory.Accumulator(AC or Acc):holds temporarily a data word(an operand or a result of ALU operation).Cpu structureAC,IBR is not necessary for connection Connection for da

9、ta transferring3.2 computer function Instruction Cycle page53Two steps(of an INSTRUCTION cycle):Fetch (取指令)Execute (执行指令)Fetch Cycle(Fetch subcycle)page54Program Counter(PC)holds address of next instruction to fetchProcessor fetches instruction from memory location pointed to by PCIncrement PCUnless

10、 told otherwiseInstruction loaded into Instruction Register(IR)Processor interprets instruction and performs required actions(issues control signals)Execute Cycle(or Execute subcycle)Processor-memorydata transfer between CPU and main memoryProcessor-I/OData transfer between CPU and I/O moduleData pr

11、ocessingSome arithmetic or logical operation on dataControlAlteration of sequence of operationse.g.jumpCombination of aboveInstruction format page550001 1001 0100 0000=1 940H Means Load data to from 940H of Memory0101 1001 0100 0001=5 941H Means Add AC with data from 941H 0010 1001 0100 0010=2 942HM

12、eans Store data in AC to 942H0111215opcodeAddress codeOpcode:0001=Load AC from Memory 0010=Store AC to Memory 0101=Add to AC from MemoryProgram consists of 3 instruction:Address instruction note300 1940 load AC from 940(M)301 5941 add to AC from 941(M)302 2941 store AC to 941(M)Address data value940

13、 0003 3941 0002 2Example of Program Execution page56The operation of Each instruction contains 2 actions with memory:Fetch instruction from memory according to PCFetch/store data from/to memory according to address in instruction.(read/write access)Thinking:memory speed is so slower,2 times of memor

14、y actions means that CPU must wait the memory performing.I.e.in PDP-11,the instructionADD B,A means fetch instruction fetch B，fetch A store to A after addition Instruction Cycle-State Diagram page57Interrupts page58Mechanism by which other modules(e.g.I/O)may interrupt normal sequence of processingP

15、rograme.g.overflow,division by zeroTimerGenerated by internal processor timerUsed in pre-emptive multi-taskingI/Ofrom I/O controllerHardware failuree.g.memory parity errorProgram Flow ControlInterrupt Cycle(or Interrupt subcycle)page59Added to instruction cycleProcessor checks for interruptIndicated

16、 by an interrupt signalIf no interrupt,fetch next instructionInterrupt Cycle(or Interrupt subcycle)page59If interrupt pending(未处理):Suspend execution of current program Save contextSet PC to start address of interrupt handler routineProcess interrupt Restore context and continue interrupted programTr

17、ansfer of Control via Interrupts page61suspendingresumingbranchingprocessingInstruction Cycle with InterruptsProgram Timing short I/O Wait page62Call I/O 1.Call I/O 2Return userinterruptReturn and wait interrupt在2a期间，CPU执行用户程序和I/O操作是同时进行的.5作为中断处理中断中断了用户程序2Interrupt handlerProgram TimingLong I/O Wait

18、Instruction Cycle(with Interrupts)-State Diagram page65Multiple Interrupts page64Disable interruptsProcessor will ignore further interrupts while processing one interruptInterrupts remain pending and are checked after first interrupt has been processedInterrupts handled in sequence as they occurMult

19、iple Interrupts Sequential page66Multiple Interrupts page64Define priorities(优先级)Low priority interrupts can be interrupted by higher priority interruptsWhen higher priority interrupt has been processed,processor returns to previous interrupt (in nest as they occur)Multiple Interrupts Nested page66T

20、ime Sequence of Multiple Interrupts page67slowestfastestmiddle3.3 interconnection structure page67All the units must be connectedDifferent type of connection for different type of unitMemoryInput/OutputCPUComputer ModulesMemory Connection page68Receives and sends dataReceives addresses(of locations)

21、Receives control signals ReadWriteTimingInput/Output Connection(1)Similar to memory from computers viewpointOutputReceive data from computerSend data to peripheralInputReceive data from peripheralSend data to computerInput/Output Connection(2)Receive control signals from computerSend control signals

22、 to peripheralse.g.spin diskReceive addresses from computere.g.port number to identify peripheralSend interrupt signals(control)CPU ConnectionReads instruction and dataWrites out data(after processing)Sends control signals to other unitsReceives(&acts on)interruptsInsertion 整数的位数确定了它的表示范围例如：三位d2d1d0

23、的表示范围为000至999共103=1000数可以推出N位十进制整数表示范围为0至10N-1，共10N个数继续：则N位二进制整数表示范围为0至2N-1，共2N个数例如：四位b3b2b1b0可表示0000至1111共24=16个数N位的二进制地址编码可以在位的二进制地址编码可以在2N个存储个存储“字字”中中确定一个确定一个“字字”-寻址范围寻址范围(addressing range)或称为或称为存储空间存储空间(memory space)3.4 Bus interconnection page69There are a number of possible interconnection sys

24、temsSingle and multiple BUS structures are most commone.g.Control/Address/Data bus(PC)e.g.Unibus(DEC-PDP)What is a Bus?A communication pathway connecting two or more devicesUsually broadcast Often groupedA number of channels in one buse.g.32 bit data bus is 32 separate single bit channelsPower lines

25、 may not be shownData BusCarries dataRemember that there is no difference between“data”and“instruction”at this levelWidth is a key determinant of performance8,16,32,64 bitAddress busIdentify the source or destination of datae.g.CPU needs to read an instruction(data)from a given location in memoryBus

26、 width determines maximum memory capacity of systeme.g.8080 has 16 bit address bus giving 64k address spaceControl BusControl and timing informationMemory read/write signalInterrupt requestClock signalsBus Interconnection SchemeBig and Yellow?What do buses look like?Parallel lines on circuit boardsR

27、ibbon cablesStrip connectors on mother boardse.g.PCISets of wiresThe operation of bus page 71some modules(Initiaors:CPU)can do 2 things:(somes just only are passtive targets:memory)Send (or write,store)Obtain the use of busSend the target address&control signal Transfer data to the target module via

28、 the data lineRequest(or fetch,read)Obtain the use of busTransfer a request control to the other module pointed by address linesWait for data from the other moduleSingle Bus ProblemsLots of devices on one bus leads to:Propagation delaysLong data paths mean that co-ordination of bus use can adversely

29、 affect performanceIf aggregate data transfer approaches bus capacityMost systems use multiple buses to overcome these problemsTraditional(ISA)(with cache)page73High Performance Bus page73Bus TypesDedicatedSeparate data&address linesMultiplexedShared lines(data&address共用，时间分前后，再加控制信号)Address valid o

30、r data valid control lineAdvantage-fewer linesDisadvantagesMore complex controlUltimate performanceBus ArbitrationMore than one module controlling the buse.g.CPU and DMA controllerOnly one module may control bus at one timeArbitration may be centralised or distributedCentralised Arbitration(集中仲裁)pag

31、e75Single hardware device controlling bus accessBus ControllerArbiterMay be part of CPU or separateDistributed Arbitration(分散仲裁)Each module may claim the busControl logic on all modulesTimingCo-ordination of events on bus(协调)Synchronous(同步)Events determined by clock signalsControl Bus includes clock

32、 lineA single 1-0 is a bus cycleAll devices can read clock lineUsually sync on leading edgeUsually a single cycle for an eventSynchronous Timing DiagramAsynchronous Timing Read DiagramAsynchronous Timing Write Diagram3.5 PCI Bus page 79Peripheral Component InterconnectionIntel released to public dom

33、ain32 or 64 bit50 linesPCI Bus Lines(required)Systems linesIncluding clock and resetAddress&Data32 time mux lines for address/dataInterrupt&validate linesInterface ControlArbitrationNot sharedDirect connection to PCI bus arbiterError linesPCI Bus Lines(Optional)Interrupt linesNot sharedCache support

34、64-bit Bus ExtensionAdditional 32 linesTime multiplexed2 lines to enable devices to agree to use 64-bit transferJTAG/Boundary ScanFor testing proceduresPCI CommandsTransaction between initiator(master)and targetMaster claims busDetermine type of transactione.g.I/O read/writeAddress phaseOne or more

35、data phasesPCI Read Timing Diagram帧A/D时钟命令字节发接*32*4接被选中PCI Bus Arbitration(参见F3.24)(page86)A请求B请求A允许B允许发接A/D帧Foreground ReadingStallings,chapter 3(all of it) fact,read the whole site! 11.page 90 problems 3.12.translate the following terms PC ,AC,MAR,MBR,IR,bus,data bus,address bus,control bus,handle

36、r,opcode,Bus arbitrate,multiplexed bus,interruptInstruction cycle,fetch cycle,execute cycle 3.PC means _.A.personal computer B.programming controllerC.program counterD.portable computerProblems 24.PC holds _.A.address of next instructionB.next instructionC.address of operandD.operand5.At the end of

37、fetch cycle,MAR holds _.A.address of instructionB.instructionC.address of operandD.operand Problems 36.Interrupt process steps are _.A.suspending,resuming,branching&processingB.branching,suspending,processing&resumingC.suspending,branching,processing&resumingD.processing,branching,resuming&suspending7.A binary number is n bits,so is can represent a value in the range between _.A.0 to n-1B.1 to nC.0 to 2n-1D.1 to 2n