常用芯片资料——2103.docx

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1、FEATURES16-Bit Sig ma-Delta ADC1. 2 MSPS Output Word Rate32/16 X Oversampling RatioLow-Pass and Band-Pass Digital FilterLinear PhaseOn-Chip 2 5V Voltage ReferenceStandby ModeFlexible Parallel or Serial InterfaceCrystal OscillatorSingle +5 V Supply16-腕 12 MSPS CMOS, Sigmar-Delta ADC AD7723FUNCTIONAL

2、BLOCK DIAGRA MavddAGNDAD77232.5V REFERENCEREF2REF1VIN(+)VIN(-)CIDMODULATORFI%RDVddDGNDUNI HALF_PWR STBYXTAL CLOCKXTAL_OFF XTAL CLKINMODE1MODE 2DGND/DB15DGND/DB14SYNCSCR/DB13DVdd/CSCFMT/RDDGND/DRDYCONTROL LOGICSLDR/DB12SLP/DB11TSI/DB10DGND/DB0FSO/DB9FSIZ SCO/ SDO/DB6 DB7 DB8DGND/ DGND/ DGND/ DOE/ SFM

3、T/DB1 DB2 DB3 DB4 DB5GENERAL DESCRIPTIONThe A D7723 is a complete 16-bit, sigma-delta ADC. The part operates from a +53 supply. The analog input is continuously sampled, eliminating the need for an external sample-and-hold. The modulator output is processed by a finite impulse response (FIR) digital

4、 filter: The on-chip filtering combined with a high oversampling ratio reduces the external antialias requirements to first order in most cases The digital filter frequency response can be program med to be either low pass or band pass.The A D7723 provides 16-bit performance for input band widths up

5、 to 460kHz at an output word rate up to 1. 2 M Hz. The sample rate, filter corner frequencies and output word rate are set by the crystal oscillator or external dock frequency.Data can be read from the device in either serial or parallel format A stereo mode allows data from two devices to share a s

6、ingle serial data line. All interface modes offer easy, high speed connections to modern digital signal processorsThe part provides an on-chip 2.5&reference. Alternatively, an external reference can be usedA power-down mode reduces the idle power consumption to 200 pW.The AD7723 is available in a 44

7、-lead PQFP package and is specified over the industrial tcm perature range from -40 to + 85.T wo input modes are provided, allowing both unipolar and bipolar input ranges.REV. 0Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assu med by

8、Analog Devices for its use, nor for any infringe ments of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.One Technology Way, P. 0. Box 9106, Norwood, MA 02062-9106, U.S. A.

9、Tel: 781/329-4700 W orld Wide Web Site: w w. analog, co mFax: 781/326-8703 Analog Devices, Inc., 1998PARALLEL MODE PIN FUNCTION DESCRIPTIONSM ne monicPin No.DescriptionDVdd/CS30Chip Select Logic InputCFMT/RD4Read Logic Input Used in conjunction with CS to read data from the parallel bus. The output

10、databus is enabled when the rising edge of CL KI N senses a logic low level on RD if CS is also low. WhenR D is sensed high, the output data bits, DB15- DBO will be high impedance.D G N D/ D R D Y5Data Ready Logic Output A falling edge indicates a new output word is available to be read fromthe outp

11、ut data register DR D Y will return high upon completion of a read operation. If a read operationdoes not occur between output updates, DR D Y will pulse high for two CL KI N cycles before the nextoutput update DR D Y also indicates when conversion results are available after a SY N C sequence.DGND/

12、DB1531Data Output Bit, (MSB)DGND/DB1432Data Output BitSCR/DB1333Data Output BitSLDR/DB1234Data Output BitSLP/DB1135Data Output BitTSI/DB1O36Data Output BitFSO/ I)B937Data Output BitSDO/DB838Data Output BitSCO/ DB740Data Output BitFSI/DB641Data Output BitSFMT/DB542Data Output BitD0E/DB443Data Output

13、BitD G N D/DB344Data Output BitD G N D/DB21Data Output BitDGND/DB12Data Output BitDGND/DBO3Data Output Bit, (LSB).SERIAL MODE PIN FUNCTION DESCRIPTIONSM ne monicPin No.DescriptionCF MT/RD4Serial Clock Format Logic Input The clock format pin selects whether the serial data, SD 0, is valid on the risi

14、ng or falling edge of the serial clock, SCO. When CF M T is logic low, serial data is valid on the falling edge of the serial clock, SCO. If C F M T is logic high, SD 0 is valid on the rising edge of SCO.DOE/ DB443Data Output Enable Logic Input. The DOE pin controls the three-state output buffer of

15、the S D 0 pin. The active state of D0E is determined by the logic level on the TSI pin. When the 1) 0E logic level equals the level on the TSI pin the serial data output, SD 0, is active. Otherwise SD 0 will be high impedance. SD 0 can be three-state after a serial data transmission by connecting DO

16、E to FSO. In normal operations, TSI and DOE should be tied low.SFMT/DB542Serial Data Format Logic Input The logic level on the SF M T pin selects the format of the FS 0 signal for Serial Mode 1. A logic low makes the FSO output a pulse, one SCO cycle wide at the beginning of a serial data transmissi

17、oa With SF M T set to a togic high, the FS 0 signal is a frame pulse that is active low for the duration of the 16-bit trans missioa For Serial Modes 2 and 3, SF M T should be tied high.FSI/DB641Frame Synchronization Logic Input The FSI input is used to synchronize the AD7723 serial output data regi

18、ster to an externed source and to allow more than one AD7723, operated from a com mon master clock, to simultaneously sample its analog input and update its output registerSCO/DB740Serial Clock OutputSD0/DB838Serial Data Output. The serial data is shifted out MSB first, synchronous with the SCO. Ser

19、ial M o de 1 data transmissions last 32 SC 0 cycles After the LSB is output, trailing zeros are output for the remaining 16 SCO cycles Serial Modes 2 and 3 data transmissions last 16 SCO cyclesFS0/DB937Frame Sync Output FSO indicates the beginning of a word trans mission on the SD 0 pin. Depending o

20、n the logic level of the SFM T pin, the FSO signal is either a positive pulse approxi mately one SCO period wide, or a irame pulse which is active low for the duration of the 16-data bit transmission.TSI/DB1O36Ti me Slot Logic Input The logic level on TSI sets the active state of the DOE pin. With T

21、SI set logic high, DOE will enable the SD 0 output buffer when it is a logic high, and vice versa TSI is used when two A D7723s are connected to the same serial data bus. When this function is not needed, TSI and DOE should be tied low.SLP/DB1135Serial Mode Low Pass/Band Pass Filter Select Input Wit

22、h SLP set logic high, the low-pass filter response is selected. A logic low selects band pass.SLDR/DB1234Serial Mode Low/High Output Data Rate Select Input With SL D R set logic high, the low data rate is selected A logic low selects the high data rata The high data rate corresponds to data at the o

23、utput of the fourth deci mation filter (Deci mate by 16). The low data rate corresponds to data at the output of the fifth deci mation filter (Deci mate by 32).SCR/DB1333Serial Clock Rate Select Input With SCR set logic low, the serial clock output frequency, SC 0, is equal to the CL KI N frequency.

24、 A logic high sets it equal to one-half the CL KI N frequency.DVdd/CS30Tie to DVDdDGND/DB1432Tie to DGND.DGND/DB1531Tie to DGND.DGND/DRDY5Tie to DGND.DGND/DBO3Tie to DGND.DGND/DB12Tie to DGND.DGND/DB21Tie to DGND.D G N D/DB344Tie to DGND.THD =20 logTERMINOLOGYSignal-to-Noise Ratio (SNR)SNR is the me

25、asured signal-tern oise ratio at the output of the ADC. The signal is the rms magnitude of the fundamental N oise is the rms sum of all of the nonfundamental signals up to half the output data rate (F(/2), excluding de. The A D C is evaluated by applying a low noises low distortion sine wave signal

26、to the input pins. By generating a Fast Fourier Transform (FFT) plot, the SNR data can then be obtained from the output spectru m.Total Har monic Distortion (T H D)T H D is the ratio of the rms sum of the harmonics to the rms value of the fundamentaL T H D is defined as:y 2+y 2+y 2+V52+V62 乙Q”Viwher

27、e V)is the rms amplitude of the fundamental and VV V 中 V5 and V6 are the rms amplitudes of the second through sixth harmonics. The THD is also derived from the FFT plot of the ADC output spectru m.Spurious Free Dyna mic Range (SFD R)Defined as the difference, in dB, between the peak spurious or harm

28、onic component in the ADC output spectrum (up to Fo/2 and excluding de) and the rms value of the fundamentaL Normally, the value of this specification will be determined by the largest harmonic in the output spectrum of the FFT. For input signals whose second harm onics occur in the stop band region

29、 of the digital filtei; the spur in the noise floor limits the SFDR.Passband RippleThe frequency response variation of the AD7723 in the defined passband frequency range.Passband FrequencyThe frequency up to which the frequency response variation is within the passband ripple specification.Cutoff Fr

30、equencyThe frequency below which the AD7723 sfrequency response will not have more than 3 dB of attenuationStopband FrequencyThe frequency above which the AD7723 sfrequency response will be within its stopband attenuation.Stopband AttenuationThe AD7723 sfrequency response will not have less than 90

31、dB of attenuation in the stated frequency bandIntegral NonlinearityT his is the maxi mu m deviation of any code from a straight line passing through the end points of the transfer function The endpoints of the transfer function are minus full scale, a point 0. 5 LSB below the first code transition (

32、100 . 00 to 100. 01 in bipolar mode, 000. . 00 to 000. . . 01 in unipolar mode) and plus full seal a point 0. 5 LSB above the last code transition (011. 10 to Oil . 11 in bipolar mode, 111. . 10 to 111. . . 11 in unipolar mode). The error is expressed in LSBs.Differential NonlinearityThis is the dif

33、ference between the measured and the ideal 1 LSB change between two adjacent codes in the ADC.Co m mon- Mode Rejection RatioThe ability of a device to reject the effect of a voltage applied to both input terminals simultaneously一often through variation of a ground level-is specified as a com mon- mo

34、de rejection ratio. C M R R is the ratio of gain for the differential signal to the gain for the com mon-mode signalUnipolax Offset ErrorU nipolar offset error is the deviation of the first code transition (10. . 000 to 10. 001) from the ideal differential voltage (VIN(+) - VIN(-)+ 0. 5 LSB) when op

35、erating in the unipolar mode.Bipolar Offset ErrorThis is the deviation of the midscale transition code (111. 11 to 000 . . 00) from the ideal differential voltage (VIN(+)- VI N (-) - Q 5 LSB) when operating in the bipolar mode.Gain ErrorT he first code transition should occur at an analog value 1/2

36、LSB above -full scale The last transition should occur for an analog value 1 1/2 LSB below the nominal full scale Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions.Typical Performance Characte

37、ristics-AD7723(AVdd = DVdd = 5 V; Ta = +25DC; CLKIN = 19.2 MHz; External +2 5 V Reference, unless otherwise noted)102110SIGNAL FREQUENCY = 98kHzMEASUREMENT BANDWIDTH = 460kHz 10090THD80SFDR70SNR 605040_28-23-18-13-8-32ANALOG INPUT LEVEL - dBFigure 9. SNR, THD and SFDR vs. Analog Input LevelRelative

38、to Full Scale (Output Data Rate = 1.2 MHz)106SIGNAL FREQUENCY = 98kHz MEASUREMENT BANDWIDTH = 300kHz 1043RD1009894THD92SNR9088-50-250255075100TEMPERATURE-!CFigure 12. SNR and THD vs. Te mperature (Output DataRate = 600 kHz)-32110SIGNAL FREQUENCY = 98kHzMEASUREMENT BANDWIDTH = 300kHz 10090THD80SFDR70

39、SNR605040-28-23-18-13-8ANALOG INPUT LEVEL - dBFigure 10. SNR, T11D and SFDR vs. Analog Input LevelRelative to Full Scale (Output Data Rate = 600 kHz)106104SFDR102100THD9896INPUT SIGNAL = 10kHz94 MEASUREMENT BANDWIDTH = 0.383 X OWR929088SNR8684100500100015002150OUTPUT WORD RATE - kHzFigure 13. SNR, T

40、11D and SFDR vs. Sampling Frequency (Deci mate by 16)102SIGNAL FREQUENCY = 98kHzMEASUREMENT BANDWIDTH = 460kHz 1003RD 98962ND94THD929088SNR8684-50-250255075100TEMPERATURE一 DCFigure 11. SNR and THD vs. Te mperature (Output DataRate = 1. 2 MHz)115INPUT SIGNAL = 10kHzMEASUREMENT BANDWIDTH = 0.5 ZOWR110

41、SFDR105100THD95SNR90 50150300450600750900OUTPUT WORD RATE - kHzFigure 14. SNR, THD and SFDR vs. Sampling Frequency (Deci mate by 32)2000 V|N(+) = V|N(-) 1800 8192 SAMPLES TAKEN16001400120010008006004002000327003270232704327063270832710 32712 32713CODEFigure 15. Histogram of Output Codes with DC Inpu

42、t (Output Data Rate = 1. 2 MHz)1.00 67108864 SAMPLES TAKEN0.80 DIFFERENTIAL MODE0.600.400.200.00-0.20-0.40-0.60-0.80-1.00 016384327684915265535CODEFigure 18. Differential Nonlinearity (Output DataRate = 600 kHz)50004500 81 ”(SAMPLES TAKEN40003500300025002000150010005000327033270432705327063270732708

43、 32709 32710CODEFigure 16. Histogram of Output Codes with DC Input (Output Data Rate = 600 kHz)1.00 67108864 SAMPLES TAKEN 0.80 DIFFERENTIAL MODE0.600.400.200.00-0.20-0.40-0.60-0.80-1.00 016384327684915265535CODEFigure 19. Integral Nonlinearity (Output DataRate = 1.2 MHz)1.00 67108864 SAMPLES TAKEN0

44、.80 DIFFERENTIAL MODE0.600.400.200.00-0.20-0.40-0.60-0.80-1.0001638432768CODE49152655351.0067108864 SAMPLES TAKEN0.80 DIFFERENTIAL MODE0.600.400.200.00-0.20-0.40-0.60-0.80-1.00016384327684915265535CODEFigure 17. Differential Nonlinearity (Output Data Rate = 1. 2 MHz)Figure 20. Integral Nonlinearity

45、(Output Data Rate = 600 kHz)225200 AIDd(HALF_POWER = 0)175150125100AIdd (HALF_POWER = 1)75-DO50250 0510152025CLOCK FREQUENCY-MHzFigure 21. Power Consu mption vs. CLKIN Frequency quantization noise, a high order modulator is employed to shape the noise spectru m, so that most of the noise energy is s

46、hifted out of the band of interest (Figure 24b).The digital filter that follows the modulator removes the large out-ofband quantization noise, (Figure 24c) while also reducing the data rate from fdKiN at the input of the filter to fcLKix/32 or fcLKiN/16 at the output of the filter; depending on the state on the MODE 1/2 pins in parallel interface mode or the pin SL D R in serial interface mode. The A D7723 output data rate is a Ettle over twice the signal bcind width, whi