EDA课后答案适用于朱正伟《EDA技术及应用》 .doc

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1、1.1、设计集成计数器74161，设计要求如下：4-BIT BINARY UP COUNTER WITH SYNCHRONOUS LOAD AND ASYNCHRONOUS CLEAR NOTEINPUTS：CLKLDNCLRNDCBAOUTPUTS：QDQCQBQARCO*RCO = QD & QC & QB & QA LIBRARY IEEE;USE _LOGIC_;USE _LOGIC_;ENTITY CNT4 ISPORT( CLK,LDN,CLRN : IN STD_LOGIC; D,C,B,A : IN STD_LOGIC; CARRY : OUT STD_LOGIC; QD,QC

2、,QB,QA : OUT STD_LOGIC );END;ARCHITECTURE A OF CNT4 IS SIGNAL DATA_IN: STD_LOGIC_VECTOR(3 DOWNTO 0);BEGIN DATA_IN0); ELSIF CLKEVENT AND CLK=1 THEN IF LDN=0 THEN CNT:=DATA_IN; ELSE CNT:=CNT+1; END IF; END IF; CASE CNT IS WHEN 1111= CARRY CARRY=0; END CASE; QA=CNT(0); QB=CNT(1); QC=CNT(2); QD=CNT(3);

3、END PROCESS; END A;1.2、设计一个通用双向数据缓冲器，要求缓冲器的输入和输出端口的位数可以由参数决定。设计要求：N BIT数据输入端口A，B。工作使能端口EN=0时双向总线缓冲器选通，DIR=1，则A=B；反之B=A。LIBRARY IEEE;USE _LOGIC_;ENTITY BIDIR ISGENERIC(N:INTEGER:=8); PORT(A,B :INOUTSTD_LOGIC_VECTOR(N-1 DOWNTO 0); EN,DIR:INSTD_LOGIC);END;ARCHITECTURE A OF BIDIR ISBEGIN PROCESS(EN,DIR)

4、 BEGIN IF EN=0 THEN AZ); BZ); ELSE IF DIR=1 THEN B=A; ELSE A=B; END IF; END IF;END PROCESS;END A;2.1、用VHDL语言编程实现十进制计数器，要求该计数器具有异步复位、同步预置功能。LIBRARY IEEE;USE _LOGIC_;ENTITY CNT_10_2 ISPORT( CLK,CLR : IN STD_LOGIC; COUNT : OUT STD_LOGIC );END;ARCHITECTURE A OF CNT_10_2 IS SIGNAL CNT_10 : INTEGER RANGE

5、0 TO 10;BEGIN PROCESS(CLK,CLR) BEGIN IF CLR=1 THEN CNT_10=0; ELSIF CLKEVENT AND CLK=1 THEN CNT_10=CNT_10+1; IF CNT_10=9 THEN CNT_10=0; COUNT=1; ELSE COUNT=0; END IF; END IF; END PROCESS;END A;2.2、设计实现一位全减器。行为描述: F_SUB4LIBRARY IEEE;USE _LOGIC_;USE _LOGIC_;ENTITY F_SUB4 ISPORT( A,B,CIN : IN STD_LOGIC;

6、 DIFF,COUT : OUT STD_LOGIC );END;ARCHITECTURE A OF F_SUB4 ISBEGIN DIFF=A XOR B XOR CIN; COUT=(NOT A AND B) OR (NOT A AND CIN) OR (B AND CIN);END A;数据流描述F_SUB1LIBRARY IEEE;USE _LOGIC_;USE _LOGIC_;ENTITY F_SUB1 ISPORT( A,B :IN STD_LOGIC; CIN :IN STD_LOGIC; DIFF,COUT : OUT STD_LOGIC );END;ARCHITECTURE

7、A OF F_SUB1 ISSIGNAL S :STD_LOGIC_VECTOR(2 DOWNTO 0);BEGIN S DIFF=0;COUT DIFF=1;COUT DIFF=1;COUT DIFF=0;COUT DIFF=1;COUT DIFF=0;COUT DIFF=0;COUT DIFF=1;COUT DIFF=X;COUT=X; END CASE; END PROCESS;END A;数据流描述F_SUB2LIBRARY IEEE;USE _LOGIC_;USE _LOGIC_;ENTITY F_SUB2 ISPORT( A,B,CIN : IN STD_LOGIC; DIFF,C

8、OUT : OUT STD_LOGIC );END;ARCHITECTURE A OF F_SUB2 ISSIGNAL S :STD_LOGIC_VECTOR(2 DOWNTO 0);SIGNAL C :STD_LOGIC_VECTOR(1 DOWNTO 0);BEGIN S=CIN&A&B; DIFF=C(1); COUT=C(0); C=00 WHEN S=000 ELSE 11 WHEN S=001 ELSE 10 WHEN S=010 ELSE 00 WHEN S=011 ELSE 11 WHEN S=100 ELSE 01 WHEN S=101 ELSE 00 WHEN S=110

9、ELSE 11 ;END A;数据流描述F_SUB3LIBRARY IEEE;USE _LOGIC_;USE _LOGIC_;ENTITY F_SUB3 ISPORT( A,B,CIN : IN STD_LOGIC; DIFF,COUT : OUT STD_LOGIC );END;ARCHITECTURE A OF F_SUB3 ISSIGNAL S :STD_LOGIC_VECTOR(2 DOWNTO 0);SIGNAL C :STD_LOGIC_VECTOR(1 DOWNTO 0);BEGIN S=CIN&A&B; DIFF=C(1); COUT=C(0); WITH S SELECT C

10、=00 WHEN 000, 11 WHEN 001, 10 WHEN 010, 00 WHEN 011, 11 WHEN 100, 01 WHEN 101, 00 WHEN 110, 11 WHEN OTHERS;END A;3.1、阅读教材P181页，例5-55并回答下列问题：（1）、该程序的功能是什么？（2）、请写出该程序所有端口的功能描述。3.2、试描述一个十进制BCD码编码器，输出使能为低电平有效。LIBRARY IEEE;USE _LOGIC_;ENTITY BIN_BCD ISPORT( BIN : IN INTEGER RANGE 0 TO 20; -ENA : IN STD_L

11、OGIC; BCD_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) );END;ARCHITECTURE A OF BIN_BCD ISBEGINBINARY_BCD : BLOCKBEGINBCD_OUT = WHEN BIN = 0 ELSE WHEN BIN = 1 ELSE WHEN BIN = 2 ELSE WHEN BIN = 3 ELSE WHEN BIN = 4 ELSE WHEN BIN = 5 ELSE WHEN BIN = 6 ELSE WHEN BIN = 7 ELSE WHEN BIN = 8 ELSE WHEN BIN = 9 ELSE

12、 WHEN BIN = 10 ELSE WHEN BIN = 11 ELSE WHEN BIN = 12 ELSE WHEN BIN = 13 ELSE WHEN BIN = 14 ELSE WHEN BIN = 15 ELSE WHEN BIN = 16 ELSE WHEN BIN = 17 ELSE WHEN BIN = 18 ELSE WHEN BIN = 19 ELSE WHEN BIN = 20 ELSE ;END BLOCK;END A;4.1、读教材P151页，例5-32的程序，并回答以下问题：（1）请画出该程序所描述的电路结构图，要求标清楚每一个端口以及内部信号。（串入/串出移

13、位寄存器）4.2、用VHDL语言设计一个能够实现任意整数进制的计数器。LIBRARY IEEE;USE _LOGIC_;-*ENTITY FREQDV_N IS GENERIC(N:INTEGER:=6); PORT( CLK :IN STD_LOGIC; CLK_DIV : OUT STD_LOGIC );END;ARCHITECTURE A OF FREQDV_N IS SIGNAL CNT : INTEGER RANGE 0 TO N;BEGIN PROCESS(CLK) BEGIN IF RISING_EDGE(CLK) THEN IF CNT=0 THEN CNT=N-1; CLK_

14、DIV=1; ELSE CLK_DIV=0; CNT=CNT-1; END IF; END IF; END PROCESS;END A;5.1、设计一个序列信号发生器，要求能够循环输出序列“”。LIBRARY IEEE;USE _LOGIC_;USE _LOGIC_;ENTITY RS_1 ISPORT( CP,S,R : IN STD_LOGIC; Q,NQ : OUT STD_LOGIC );END;ARCHITECTURE A OF RS_1 ISSIGNAL S1,R1,Q1,NQ1:STD_LOGIC;BEGIN S1=S NAND CP; R1=R NAND CP; Q1=S1 N

15、AND NQ1; NQ1=R1 NAND Q1; Q=Q1; NQ=NQ1;END A;5.2、设计一个带复位端、置位端、CP下降沿触发的JK触发器。LIBRARY IEEE;USE _LOGIC_;USE _LOGIC_;ENTITY JKFF ISPORT( J,K,RST,CLR : IN BIT; CLK : IN BIT; Q,NQ : OUT BIT );END;ARCHITECTURE A OF JKFF ISSIGNAL Q_S,NQ_S : BIT;BEGIN PROCESS(J,K,RST,CLR,CLK) BEGIN IF RST=1 THEN Q_S=1; NQ_S=0

16、; ELSIF CLKEVENT AND CLK=0 THEN IF CLR=1 THEN Q_S=0; NQ_S=1; ELSIF J=0 AND K=1 THEN Q_S=0; NQ_S=1; ELSIF J=1 AND K=0 THEN Q_S=1; NQ_S=0; ELSIF J=1 AND K=1 THEN Q_S=NOT Q_S; NQ_S=NOT NQ_S; END IF; ELSE NULL; END IF; Q=Q_S; NQ=NQ_S;END PROCESS;END A;6.1、用VHDL语句描述一个三态输出的双4选一的数据选择器，其地址信号共用，且各有一个低电平有效的使能

17、端。LIBRARY IEEE;USE _LOGIC_;ENTITY DUAL_MUX_41 ISPORT( A,B,C,D : IN STD_LOGIC; ENA_N,ENB_N : IN STD_LOGIC; S : IN STD_LOGIC_VECTOR(1 DOWNTO 0); OUTA,OUTB : OUT STD_LOGIC );END;ARCHITECTURE A OF DUAL_MUX_41 IS SIGNAL P,Q : STD_LOGIC_VECTOR(2 DOWNTO 0);BEGIN P=ENA_N & S; Q=ENB_N & S; WITH P SELECT OUTA

18、=A WHEN 000, B WHEN 001, C WHEN 010, D WHEN 011, Z WHEN OTHERS; WITH Q SELECT OUTB=A WHEN 000, B WHEN 001, C WHEN 010, D WHEN 011, Z WHEN OTHERS; END A;6.2、用并行信号赋值语句实现38译码器。LIBRARY IEEE; USE _LOGIC_; ENTITY DECODER38 IS PORT(A,B,C,G1,G1A,A2B:IN STD_LOGIC; Q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0); END DECO

19、DER38; ARCHITECTURE BEHAVE38 OF DECODER38 IS SIGNAL INDA: STD_LOGIC_VECTOR(2 DOWNTO 0); BEGIN INDAQQQQQQQQQ=XXXXXXXX; END CASE; ELSE Q=; END IF; END PROCESS;END BEHAVE38;7.1、用并行信号赋值语句实现8选一数据选择器，要求有工作使能端。LIBRARY IEEE; USE _LOGIC_; ENTITY MUX8 IS PORT(D0,D1,D2,D3,D4,D5,D6,D7:IN STD_LOGIC_VECTOR(7 DOWN

20、TO 0); S0,S1,S2:IN STD_LOGIC; Q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0); END MUX8;ARCHITECTURE BEHAVE OF MUX8 IS SIGNAL S: STD_LOGIC_VECTOR(2 DOWNTO 0);BEGIN S =S2&S1&S0; WITH S SECLECT D =D0 WHEN 000, D1 WHEN 001, D2 WHEN 010, D3 WHEN 011, D4 WHEN 100, D5 WHEN 101, D6 WHEN 110, D7 WHEN 111, XWHEN OTHERS;E

21、ND BEHAVE;7.2、用VHDL语言设计实现输出占空比为50%的1000分频器。LIBRARY IEEE;USE _LOGIC_;ENTITY DIV_1000 ISPORT( CLK ,CLR: IN STD_LOGIC; DIV : OUT STD_LOGIC );END;ARCHITECTURE A OF DIV_1000 ISSIGNAL Q : STD_LOGIC;BEGIN DIV=Q; PROCESS(CLK,CLR) VARIABLE CNT : INTEGER RANGE 0 TO 499; BEGIN IF CLR=1 THEN CNT:=0; Q=0; ELSIF

22、RISING_EDGE(CLK) THEN IF CNT=499 THEN CNT:=0; Q=NOT Q; ELSE CNT:=CNT+1; END IF; END IF; END PROCESS;END A;8.1、设计一个一位全减器。LIBRARY IEEE;USE _LOGIC_;USE _LOGIC_;ENTITY F_SUB3 ISPORT( A,B,CIN : IN STD_LOGIC; DIFF,COUT : OUT STD_LOGIC );END;ARCHITECTURE A OF F_SUB3 ISSIGNAL S :STD_LOGIC_VECTOR(2 DOWNTO 0)

23、;SIGNAL C :STD_LOGIC_VECTOR(1 DOWNTO 0);BEGIN S=CIN&A&B; DIFF=C(1); COUT=C(0); WITH S SELECT C=00 WHEN 000, 11 WHEN 001, 10 WHEN 010, 00 WHEN 011, 11 WHEN 100, 01 WHEN 101, 00 WHEN 110, 11 WHEN OTHERS;END A;8.2、用元件例化语句描述一个四位的全减器。LIBRARY IEEE;USE _LOGIC_;USE _LOGIC_;ENTITY F_SUB4_1 ISPORT( A,B : IN S

24、TD_LOGIC_VECTOR(3 DOWNTO 0); CIN : IN STD_LOGIC; DIFF: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); COUT: OUT STD_LOGIC );END;ARCHITECTURE A OF F_SUB4_1 ISCOMPONENT F_SUB1 IS PORT( A,B,CIN : IN STD_LOGIC; DIFF,COUT : OUT STD_LOGIC ); END COMPONENT;SIGNAL C :STD_LOGIC_VECTOR(3 DOWNTO 0);BEGIN U1: F_SUB1 PORT MA

25、P(A(0),B(0),CIN,DIFF(0),C(0); U2: F_SUB1 PORT MAP(A(1),B(1),C(0),DIFF(1),C(1); U3: F_SUB1 PORT MAP(A(2),B(2),C(1),DIFF(2),C(2); U4: F_SUB1 PORT MAP(A(3),B(3),C(2),DIFF(3),C(3); COUT=C(3);END A;9.1、利用生成语句描述一个由N个一位全减器构成的N位减法器，N的默认值为4。LIBRARY IEEE;USE _LOGIC_;USE _LOGIC_;ENTITY F_SUB4_2 ISGENERIC (N :

26、INTEGER := 4);PORT( A,B : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0); CIN : IN STD_LOGIC; DIFF: OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0); COUT: OUT STD_LOGIC );END;ARCHITECTURE A OF F_SUB4_2 ISCOMPONENT F_SUB1 IS PORT( A,B,CIN : IN STD_LOGIC; DIFF,COUT : OUT STD_LOGIC ); END COMPONENT;SIGNAL C :STD_LOGIC_VECTOR(N

27、DOWNTO 0);BEGIN C(0)=CIN; N1: FOR I IN 0 TO N-1 GENERATE U1: F_SUB1 PORT MAP(A(I),B(I),C(I),DIFF(I),C(I+1); END GENERATE; COUT=C(N);END A;9.2、设计一个模为60、具有异步复位、同步置数功能的8421码计数器。LIBRARY IEEE;USE _LOGIC_;USE _LOGIC_;ENTITY COUNT_60 ISPORT( CLK ,CLR,PST: IN STD_LOGIC; A : IN STD_LOGIC_VECTOR(5 DOWNTO 0);

28、Q : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); CO: OUT STD_LOGIC );END;ARCHITECTURE A OF COUNT_60 ISSIGNAL CNT: STD_LOGIC_VECTOR(5 DOWNTO 0);BEGIN Q=CNT; PROCESS(CLK,CLR,PST,A) BEGIN IF CLR=1 THEN CNT0); CO=0; ELSIF RISING_EDGE(CLK) THEN IF PST=1 THEN CNT=A; ELSIF CNT=59 THEN CNT0); CO=1; ELSE CNT=CNT+1; CO6

29、,M=10) PORT MAP(A=TRIGGER_IN,CLK=CLK,Y=MONO_OUT);END A;10.2、设计实现一个83优先编码器。LIBRARY IEEE;USE _LOGIC_;USE _LOGIC_;ENTITY MONO_TRIGGER IS -非可重复触发单稳态触发器GENERIC(N:INTEGER:=5; -单稳态定时参数 M:INTEGER:=10); -定义定时参数取值范围PORT( A,CLK: IN STD_LOGIC; Y : OUT STD_LOGIC );END;ARCHITECTURE A OF MONO_TRIGGER ISTYPE STATE

30、IS(ST0,ST1,ST2);SIGNAL CURRENT_STATE,NEXT_STATE : STATE;SIGNAL Q:STD_LOGIC;BEGIN REG:PROCESS(A,CLK) BEGIN IF CLKEVENT AND CLK=1 THEN CURRENT_STATE IF A=0 THEN NEXT_STATE=ST0; Y=0; ELSE NEXT_STATE IF Q=1 THEN NEXT_STATE=ST2; Y=0; ELSE NEXT_STATE=ST1; Y IF A=1 THEN NEXT_STATE=ST2; Y=0; ELSE NEXT_STATE=ST0; Y NEXT_STATE=ST0; END CASE; END PROCESS; AUX_COUNT:PROCESS(CURRENT_STATE,CLK) VARIABLE COUNT : INTEGER RANGE 0 TO M; BEGIN IF CLKEVENT AND CLK=1 THEN IF CURRENT_STATE/=ST1 THEN COUNT:=N; ELSE COUNT:=COUNT-1; EN