JMB585 Datasheet (Rev. 1.1)原版完整文件.docx

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1、DATASHEETJMB585PCIe Gen3x2 to 5 SATA 6Gb/s BridgeDocument No.: PDS-18001/ Revision: 1.1 / Date: 12/14/2018JMicron Technology Corporation1F, No. 13, Innovation Road 1, Science-Based Industrial Park, Hsinchu, Taiwan 300, R.O.C.Tel: 886-3-5797389Fax: 886-3-5799566Website: JMB585DatasheetCopyright 2018,

2、 JMicron Technology Corp. All Rights Reserved. Printed in Taiwan 2018JMicron and the JMicron Logo are trademarks of JMicron Technology Corporation in Taiwan and/or other countries. Other company, product and service names may be trademarks or service marks of others.All information contained in this

3、 document is subject to change without notice. The products described in this document are NOT intended for use implantation or other life supports application where malfunction may result in injury or death to persons. The information contained in this document does not affect or change JMicrons pr

4、oduct specification or warranties. Nothing in this document shall operate as an express or implied license or environments, and is presented as an illustration. The results obtained in other operating environments may vary.THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED ON AN “AS IS” BASIS. I

5、n no event willJMicron be liable for damages arising directly or indirectly from any use of the information contained in this document.For more information on JMicron products, please visit the JMicron web site at http:/www.JM or send e-mail to sales. For product application support, please send e-m

6、ail to fae.JMicron Technology Corporation1F, No.13, Innovation Road 1, Science-Based Industrial Park, Hsinchu, Taiwan 300, R.O.C. Tel: 886-3-5797389Fax: 886-3-5799566Revision 1.1vDocument No.: PDS-18001The information contained in this document is the exclusive property of JMicron Technology Corpora

7、tion and shall not be used, collected, reproduced, distributed and/or disclosed in whole or in part without prior written permission of JMicron Technology Corporation.Revision HistoryRevision NumberEffective DateDescription of RevisionAuthorReferenceDescription of the Change0.102/26/2018-Draft relea

8、seSteven Lin0.210/05/2018-1. rename JMS585 to JMB5852. remove GPIO03. rename Signal Name in 5 Package pin-out4. swap PCIe Lane0 and Lane1MD Lin1.011/01/2018Chapter 7Update Electrical characteristicsMD Lin1.112/14/2018Change core power to 1.25VMD LinTable of ContentsRevision HistoryiiTable of Content

9、siiiFigure ListivTable Listv1 Introduction12 Features23 Block diagram34 Package dimension45 Package pin-out55.1 Pin assignment55.2 Pin type definition65.3 Pin description75.3.1 PCIe interface75.3.2 SATA Gen 3 interface85.3.3 Crystal interface95.3.4 Control and GPIO interface95.3.5 Power supply116 Cl

10、ock and reset126.1 Crystal input127 Electrical characteristics137.1 Absolute maximum rating137.2 Operating voltage and temperature137.3 External clock source conditions147.4 Power dissipation147.4.1 PCIe to SATA mode147.5 I/O DC characteristics157.6 Power-on sequence168 Product naming rule and ident

11、ification188.1 Format of the part number188.2 Explanation of the part number188.3 Top mark19Figure ListFigure 1 Block diagram3Figure 2 Package outline drawing of QFN76 9x94Figure 3 76-Pin assignment of JMB5855Figure 4 Power-on sequence16Figure 5 Format of the part number18Figure 6 Illustration of de

12、vice top mark19Table ListTable 1 Pin type definition6Table 2 Pin description PCIe interface7Table 3 Pin description SATA 3.1 Gen 38Table 4 Pin description Crystal interface9Table 5 Pin description Control and GPIO interface9Table 6 Pin description Power supply interface11Table 7 Crystal electrical s

13、pecification12Table 8 Absolute maximum rating13Table 9 Operating voltage and temperature13Table 10 External clock source conditions14Table 11 Power dissipation Operation with PCIe L0 state14Table 12 Power dissipation Idle with PCIe L0 state14Table 13 Power dissipation Suspend with PCIe L2 state15Tab

14、le 14 I/O DC characteristics15Table 15 Power-on timing requirements17Table 16 Explanation of the part number18JMB585Datasheet1 IntroductionThe JMB585 is a bridge controller between the PCIe host and the storage devices with SATA/AHCI interface. Its upstream port provides a PCIe which data transmissi

15、on rate for PCIe Gen 3x2 specification. Meanwhile, its downstream port can connect to SATA/AHCI storage devices, such as a solid-state drive (SSD). The data speed of each port for the SATA port can arrive at 6Gb/s.Also, the JMB585 SATA Host provides five ports and supports Port Multiplier. JMB585 su

16、pports command-based switching (CBS) and FIS (Frame Information Structure)-based switching (FBS). The default communication method between the SATA Host and the port Multiplier is CBS. FBS allows the Host controller to issue multiple commands that send and receive data simultaneously from any drive.

17、The JMB585 supports TRIM to the SSD and can transmit and receive data by both of AHCI mode and legacy IDE mode to and from the host respectively.JMB585 is highly integrated with JMicron PCI Express and SATA self-designed PHYs.Finally, the JMB585 is a new product that almost reaches PCIe Gen3x2 line

18、bandwidth. JMB585 can be applied on PC. Mobile, severs, IPC, consumer electrical devices, storage device, and NVR/DVR system.Revision 1.119Document No.: PDS-18001The information contained in this document is the exclusive property of JMicron Technology Corporation and shall not be used, collected, r

19、eproduced, distributed and/or disclosed in whole or in part without prior written permission of JMicron Technology Corporation.2 FeaturesGeneral Featuresn 15 GPIOs for customization.n SPI interface for external SPI Flash (Option ROM).n Supports Windows 7, Windows 10 and Linux-base OSn Supports 3.3V

20、I/O and 1.25V core power.n 25MHz external crystal.n 76-pin (2 lane PCIe to 5 SATA port) package.PCI Express Featuresn Supports up to two lane of PCI Express.n Complies with PCI Express Base Specification Revision 3.1a.n Supports PCIe link layer power saving mode.n 100MHz differential PCI Express ref

21、erence clock in.SATA Featuresn Supports 5 SATA port.n Supports command-based and FIS-based for Port Multiplier.n Complies with SATA Specification Revision 3.2.n Supports AHCI mode and IDE programming interface.n Supports Native Command Queue (NCQ).n Supports SATA link power saving mode (partial and

22、slumber)n Supports SATA plug-in detection capable.n Supports drive power control and staggered spin-up.n Supports SATA Partial / Slumber power management state.3 Block diagramFigure 1 Block diagram4 Package dimensionFigure 2 Package outline drawing of QFN76 9x95 Package pin-out5.1 Pin assignmentFigu

23、re 3 76-Pin assignment of JMB5855.2 Pin type definitionTable 1 Pin type definitionPin typeDefinitionAAnalogDDigitalIInputOOutputPPowerIOBi-directionalLInternal weak pull-lowHInternal weak pull-high (Max. 85 kW, Typical 54 kW, Min. 36 kW)5.3 Pin description5.3.1 PCIe interfaceTable 2 Pin description

24、PCIe interfaceSignal NameQFN 76TypeDescriptionP_RXN026AIPCIe Port RX- Signal of Lane 0P_RXP027AIPCIe Port RX+ Signal of Lane 0P_TXN029AOPCIe Port TX- Signal of Lane 0A 200 nF capacitor should be connected between this pin and PCIe connector.P_TXP030AOPCIe Port TX+ Signal of Lane 0A 200 nF capacitor

25、should be connected between this pin and PCIe connector.P_REXT31AIExternal Reference ResistanceA 12 kW1% external resistor should be connected to this pin.P_RXN133AIPCIe Port RX- Signal of Lane 1P_RXP134AIPCIe Port RX+ Signal of Lane 1P_TXN136AOPCIe Port TX- Signal of Lane 1A 200 nF capacitor should

26、 be connected between this pin and PCIe connector.P_TXP137AOPCIe Port TX+ Signal of Lane 1A 200 nF capacitor should be connected between this pin and PCIe connector.P_REFCLKP24DIDifferential Clock P100Mhz reference clock from Host.P_REFCLKN23DIDifferential Clock N100Mhz reference clock from Host.P_R

27、STN22DIPCIE Reset from HostP_CLKREQ21DIOThis is for L1 substate5.3.2 SATA Gen 3 interfaceTable 3 Pin description SATA 3.1 Gen 3Signal NameQFN 76TypeDescriptionS_RXP040AISATA Port0 RX+ SignalS_RXN041AISATA Port0 RX- SignalS_TXN043AOSATA Port0 TX- SignalA 10 nF capacitor should be connected between th

28、is pin and SATA connector.S_TXP044AOSATA Port0 TX+ SignalA 10 nF capacitor should be connected between this pin and SATA connector.S_RXP146AISATA Port1 RX+ SignalS_RXN147AISATA Port1 RX- SignalS_TXN149AOSATA Port1 TX- SignalA 10 nF capacitor should be connected between this pin and SATA connector.S_

29、TXP150AOSATA Port1 TX+ SignalA 10 nF capacitor should be connected between this pin and SATA connector.S_RXP252AISATA Port2 RX+ SignalS_RXN253AISATA Port2 RX- SignalS_TXN255AOSATA Port2 TX- SignalA 10 nF capacitor should be connected between this pin and SATA connector.S_TXP256AOSATA Port2 TX+ Signa

30、lA 10 nF capacitor should be connected between this pin and SATA connector.S_RXP364AISATA Port3 RX+ SignalS_RXN365AISATA Port3 RX- SignalS_TXN367AOSATA Port3 TX- SignalA 10 nF capacitor should be connected between this pin and SATA connector.S_TXP368AOSATA Port3 TX+ SignalA 10 nF capacitor should be

31、 connected between this pin and SATA connector.S_RXP470AISATA Port4 RX+ SignalS_RXN471AISATA Port4 RX- SignalS_TXN473AOSATA Port4 TX- SignalA 10 nF capacitor should be connected between this pin and SATA connector.S_TXP474AOSATA Port4 TX+ SignalA 10 nF capacitor should be connected between this pin

32、and SATA connector.5.3.3 Crystal interfaceTable 4 Pin description Crystal interfaceSignal NameQFN 76TypeDescriptionXIN59AICrystal Input/Oscillator InputIt is connected to a 25MHz crystal or crystal oscillator. The variation range should be 30ppm. And the input voltage range is 3.3V5%.XOUT60AOCrystal

33、 OutputIt is connected to a crystal. While crystal oscillator is applied, this pin should be reserved for No Connection (NC). The output variation range is around 30ppm (input dependent). And the output voltage range is 3.3V5% (input dependent).5.3.4 Control and GPIO interfaceTable 5 Pin description

34、 Control and GPIO interfaceSignal NameQFN 76TypeDescriptionXTSTN2DIMP Test Mode EnableSchmitt trigger input pin. This pin is reserved for IC mass production testing. Keep this pin to logic “1” in normal operation.GPIO119DOSPI SI : SPI Flash SI Pin.GPIO218DOSPI CK : SPI Flash CK PinGPIO317DOSPI WP# :

35、 SPI Flash WP# PinSignal NameQFN 76TypeDescriptionGPIO415DISPI SO : SPI Flash SO PinGPIO513DOSPI CE# : SPI Flash CE# PinGPIO64DOSATA0 LED : SATA Port 0 PWM (PHY Ready / Link Busy / SleepDim)GPIO73DOSATA1 LED : SATA Port 1 PWM (PHY Ready / Link Busy / Sleep Dim)GPIO876DOSATA2 LED : SATA Port 2 PWM (P

36、HY Ready / Link Busy / Sleep Dim)GPIO914DOSATA3 LED : SATA Port 3 PWM (PHY Ready / Link Busy / Sleep Dim)GPIO1011DOSATA4 LED : SATA Port 4 PWM (PHY Ready / Link Busy / Sleep Dim)GPIO1110DIOGPO11 : General Purpose I/OGPIO129DIOGPO12 : General Purpose I/O.GPIO138DIOGPO13 : General Purpose I/OGPIO147DI

37、OGPO14 : General Purpose I/OGPIO156DIOGPO15 : General Purpose I/O5.3.5 Power supplyTable 6 Pin description Power supply interfaceSignal NameQFN 76TypeDescriptionVCCK5,16, 38,62, 75PI1.25V core power supplyVCCO1,14PI3.3V I/O power supplyP_AVDDL25,28,32,35PIAnalog 1.25V power supply for PCIeS_AVDDL39,

38、42,45,48,51,54,63,66,69,72PIAnalog 1.25V power supply for SATAXAVDDL58PIAnalog 1.25V power supply for crystal oscillatorXAVDDH61PIAnalog 3.3V power supply for crystal oscillator6 Clock and reset6.1 Crystal inputSingle crystal input (25MHz) is needed.Table 7 Crystal electrical specificationParameterS

39、ymbolMinTypicalMaxUnitCrystal Frequencyfclk25MHzLong term stability (Crystal Only)fMAX_Crystal-3030ppm7 Electrical characteristics7.1 Absolute maximum ratingTable 8 Absolute maximum ratingParameterSymbolConditionMinMaxUnitDigital 3.3VVCCO(ABS)-0.5VCCO+0.5VDigital 1.25VVCCK(ABS)-0.5VCCK+0.5VAnalog 3.

40、3VXAVDDH-0.5XAVDDH+0.5VAnalog 1.25VXAVDDL(ABS)-0.5XAVDDL+0.5VAnalog 1.25VS_AVDDL(ABS)-0.5S_AVDDL+0.5VAnalog 1.25VP_AVDDL(ABS)-0.5P_AVDDL+0.5VDigital I/O input voltageVI(D)-0.5VCCO+0.5VStorage temperatureTSTORAGE-40150oC7.2 Operating voltage and temperatureTable 9 Operating voltage and temperaturePar

41、ameterSymbolConditionMinTypicalMaxUnitDigital 3.3VVCCO3.03.33.6VDigital 1.25VVCCK1.201.251.30VAnalog 3.3VXAVDDH3.03.33.6VAnalog 1.25VXAVDDL S_AVDDLP_AVDDL1.201.251.30VDigital I/O input voltageVI(D)3.03.33.6VAmbient operation temperatureTA070oCJunction TemperatureTJ125oC7.3 External clock source cond

42、itionsTable 10 External clock source conditionsParameterSymbolConditionMinTypicalMaxUnitExternal reference clock25MHzClock Duty Cycle455055%7.4 Power dissipation7.4.1 PCIe to SATA mode7.4.1.1 Operation with PCIe L0 stateTable 11 Power dissipation Operation with PCIe L0 stateParameterSymbolConditionMinTypicalMaxUnitDigital 3.3VVCCOOperate 3.3V1mADigital 1.25VVCCKOperate 1.25V270mAAnalog 3.3VXAVDDHOperate 3.3V1mAAnalog 1.25V